Motorola Corporation

Other

Pern Shaw

Fuad H Musa

Stephen J Kreinick

Stephen P Robb

Michael F Wiles

Donald L Tietjen

Floyd E Anderson

Stanley E Groves

Lewis E Terry

Thomas G Gunter

Paul D Shannon

Duane W Cawthron

Sharon Lamb

An integrated circuit having a microprocessor core interfaced to large power transistors is described. This integrated circuit provides the capability to intelligently control and drive loads requiring currents exceeding 250 milli amps. The large power transistors are built in a technology compatible with the microprocessor core technology resulting in a more readily manufacturable circuit. The microprocessor core is layed out in a manner which provides the greatest distance between the most heat sensitive microprocessor core circuits and the power devices. On chip temperature sensing and feedback is provided for junction temperature monitoring and control.

Microprocessor having high current drive and feedback for temperature

Microprocessor having high current drive

A mode selection circuit is disclosed which is suitable for configuring a data processor at the time at which the data processor is initialized with a reset signal. Mode selection latches are coupled to terminals normally used as an input/output port for the data processor and the latches are clocked with a signal generated by a level detector circuit which senses the reset signal. The mode selection latches are programmed by applying appropriate logic levels to the terminals of the input/output port at the time at which the data processor is being reset. The circuitry is adapted for allowing the connection of a diode from a terminal of the input/output port to the reset terminal of the data processor in order to program a low logic level into the corresponding mode detection latch.

Programmable mode select by reset

A universal bus interface circuit can be used in conjunction with either synchronous or asynchronous bus systems. An input terminal is monitored to determine if the bus is synchronous or asynchronous. If the bus is asynchronous, a synchronization circuit generates a synchronous control signal for internal use from an asynchronous select signal. The synchronization circuit also generates an asynchronous hand-shake or acknowledge signal which is applied to the input terminal to indicate completion of the operation. The input terminal is monitored by a host processor.

Universal interface circuit for synchronous and asynchronous buses

A single-chip microcomputer comprises a CPU (1), a RAM (2), a ROM (3), a timer (4), serial I/O communication logic (5), four I/O ports (11-14) and various power supply, clock, and control inputs. One of the I/O ports (13) is user programmable by application of specific signals to mode selection pins (P20-22) for configuration in several possible ways. The programmable port comprises a plurality of lines which each may be individually programmed as input or output lines to peripheral equipment associated with the microcomputer. Alternatively, the port lines can be programmed to serve as a bidirectional data bus to external memory. Alternatively, the port lines can be programmed to be multiplexed data and address lines to external memory. Bus arbitration logic is provided to route data to the CPU from either on-chip memory or external memory.

Microcomputer with programmable multi-function port

A subtractor for use in a digital to digital converter has fast response and uses an operational amplifier. The fast response is achieved by varying current flow in associated circuits. An analog input controls current flow through a first portion of the circuitry and a voltage reference controls current flow through a second portion of the circuit. The total current flow through the first and second portions of the circuit is provided by a current source. The analog input is coupled to a first input of the operational amplifier and the voltage reference is coupled to a second input of the operational amplifier. A first logarithmic impedance is coupled between the first input of the operational amplifier and the output of the operational amplifier. A second logarithmic impedance is coupled between the second input of the operational amplifier and a bias voltage. The bias voltage is used to provide a predetermined biased voltage at the output of the operational amplifier.

High-speed voltage subtractor

A pulse generating circuit is coupled to an address decoder to provide the address enable signal to the address decoder. An input pulse is provided to the pulse generating circuit and the output of the pulse generating circuit is coupled to the address decoder. The output of the pulse generating circuit keeps the address decoder enabled until the trailing edge of the input pulse. Internal to the pulse generating circuit the input pulse is connected to a delay. The output of the delay is connected to a first NOR gate. Another input of the first NOR gate receives the input pulse. The output of the first NOR gate is connected to a second NOR gate. Another input of the second NOR gate also receives the input pulse. The output of the second NOR gate is the output of the pulse generating circuit which is coupled to the address decoder. The pulse generating circuit provides a momentary output pulse at the trailing edge of the input pulse to momentarily inhibit the address decoder. The pulse generating circuit is particularly useful, in a microprocessor having an on-chip RAM, to inhibit the RAM address decoder at the trailing edge of a signal derived from a microprocessor clock thereby virtually eliminating instability problems of the RAM.

RAM Address enable circuit for a microprocessor having an on-chip RAM

In a high speed synchronizing circuit, the rising edge of an asynchronous input signal is used to set an input RS flip-flop. First and second latch registers monitor the input RS flip-flop. Each latch register generates a reset signal before a change in the logic level of the system clock for resetting the input RS flip-flop. The reset pulses are very narrow which enables the RS flip-flop to be quickly conditioned to receive the next asynchronous signal.

High speed synchronization circuit

There is provided a voltage level detecting circuit useful as power-up/power-down voltage indicator for a field effect transistor integrated circuit. A constant voltage reference generator is provided by a depletion type transistor in series with two enhancement type transistors coupled between power supply terminals of the integrated circuit chip. Each of the enhancement type transistors have their gate electrodes connected to their drain electrodes while the depletion type transistor has its gate electrode connected to the more negative or reference terminal of the power supply voltage. A constant voltage output is taken from between the junction of one of the enhancement mode transistors and the depletion type transistor. This constant voltage output can be compared against a voltage obtained from a voltage divider circuit which provides an output that varies in accordance with variations in the power supply. The voltage level detector circuit is particularly useful in microprocessors and microcomputer integrated circuit chips.

FET Voltage level detecting circuit

An analog-to-digital converter includes a first and a second comparator. The first comparator generates a plurality of quantizing outputs defining voltage gaps and also has first and second reference current outputs whose magnitudes are representative of which voltage gap encompasses the analog input voltage and a third reference current output whose magnitude is representative of the voltage gap width. A first encoder receives the quantizing outputs of the first comparator and generates a binary number which represents which of the voltage gaps the analog input voltage is encompassed by. The reference current outputs of the first comparator are input to a reference voltage level shifting circuit whose shifted reference output voltage is provided as an input to a second comparator which compares the analog input with a plurality of internal reference voltages which form a second continuous range of voltage gaps. The second comparator has a plurality of outputs, one corresponding to each of the voltage gaps encompassed by the reference voltages in the second comparator. A second encoder receives as inputs the outputs of the second comparator and generates a binary output which represents the least significant bit group of the analog input voltage.

Serial-parallel analog-to-digital converter using voltage level shifting

An analog-to-digital converter includes a first and a second comparator each of which receives an analog input. The first comparator generates a plurality of reference voltages which establish a first continuous range of voltage gaps. The first comparator has a plurality of quantizing outputs, one of which will be at a logical one and the rest of which will be at logical zeros in order to indicate which of the voltage gaps encompasses the analog input voltage. The first comparator also has first and second reference current outputs whose magnitudes are representative of which voltage gap encompasses the analog input voltage and a third reference current output whose magnitude is representative of the voltage gap width. A first encoder receives the quantizing outputs of the first comparator and generates a binary number which represents which of the voltage gaps the analog input voltage is encompassed by and which constitutes the most significant bit group of the binary digital representation of the analog input voltage. The reference current outputs of the first comparator are input to a reference voltage level shifting circuit whose output voltage represents the voltage difference between a first boundary of the voltage gap which encompasses the analog input voltage and the maximum reference voltage value associated with the first comparator. The reference voltage level shifting output voltage is produced concurrently with the action of the first encoder, thereby providing overlapping operations for increased conversion speeds. This shifted reference voltage is provided as an input to a second comparator which compares the analog input with a plurality of internal reference voltages which form a second continuous range of voltage gaps. The second comparator has a plurality of outputs, one corresponding to each of the voltage gaps encompassed by the reference voltages in the second comparator. The second comparator produces a logical one on an output corresponding to the particular voltage gap defined by the shifted reference voltage. A second encoder receives as inputs the outputs of the second comparator and generates a binary output which represents the least significant bit group of the analog input voltage. In combination, the output of the first encoder and the output of the second encoder form a binary digital representation of the analog input voltage, including the most significant bits and the least significant bits thereof.

Serial parallel analog-to-digital converter using voltage level shifting

An analog-to-digital converter includes a first comparator which receives an analog input. The first comparator generates a plurality of reference voltages which establish a first continuous range of voltage gaps. The first comparator has a plurality of quantizing outputs, one of which will be at a logical one and the rest of which will be at logical zeros in order to indicate which of the voltage gaps encompasses the analog input voltage. The first comparator also has a reference current output whose magnitude is representative of which voltage gap encompasses the analog input voltage. A first encoder receives the quantizing outputs of the first comparator and generates a binary number which represents which of the voltage gaps the analog input voltage is encompassed by and which constitutes the most significant bit group of the binary digital representation of the analog input voltage. A voltage subtractor circuit receives as inputs the reference current output of the first comparator and the analog input. The voltage subtractor produces an output voltage which represents the voltage difference between a first boundary of the voltage gap which encompasses the analog input voltage and the value of the analog input voltage. The voltage subtractor output voltage is produced concurrently with the action of the first encoder, thereby providing overlapping operations for increased conversion speeds. This voltage is provided as an input to a second comparator which compares the output voltage produced by the voltage subtractor with a plurality of internal reference voltages which form a second continuous range of voltage gaps. The second comparator has a plurality of outputs, one corresponding to each of the voltage gaps encompassed by the reference voltages in the second comparator. The second comparator produces a logical one on an output corresponding to the particular voltage gap which encompasses the difference voltage produced by the voltage subtractor. A second encoder receives as inputs the outputs of the second comparator and generates a binary output which represents the difference voltage produced by the voltage subtractor and which constitutes the least significant bit group of the analog input voltage. In combination, the output of the first encoder and the output of the second encoder form a binary digital representation of the analog input voltage, including the most significant bits and the least significant bits thereof.

Serial-parallel analog-to-digital converter using voltage subtraction

A RAM being powered by a standby voltage supply and having control circuitry to save all or a portion of the information stored in the RAM during power up and power down is provided. A latch is used to hold an input signal just prior to power down to just after power up. The latch is coupled to read and write and word select logic so that the latch can inhibit the read and write logic as well as inhibiting the addressability of any storage cells in the retained portion of the RAM during power up and power down. Transistors having a control electrode are connected to the word select lines of the RAM and hold the word select lines near zero voltage during power up and power down to prevent information from flowing on the word select lines. The control electrodes of the transistors are connected to an output of the latch.

Ram retention during power up and power down

A high-speed voltage subtractor circuit suitable for use in a serial-parallel A/D converter uses differential current switches to select a predetermined reference voltage value as one input to a precision current matching circuit whose other input is an applied analog input signal. An output buffer circuit coupled to the current matching circuit produces an output signal equal to the difference between the analog input signal and the reference voltage value.

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Austin, TX, United States of America

Pern Shaw