Axis Ab

Per Zander

Kenny Ranerup

Jan Bengtsson

Johan Wennersten

Hans-Peter Nilsson

Mats Thulin

Ronny Ranerup

A Serial Peripheral Interface (SPI) master () and method therein for transferring data to a peripheral device in a data communication and processing system () are disclosed. The SPI master () comprises a memory () comprising a list of packets, each packet comprises data associated with a time parameter indicating at which time the data is to be transferred to the peripheral device. The time parameter is configurable. The SPI master further comprises a serial transmit and receive unit () to transfer the data in the list at a time according to the time parameter associated with the data.

Serial peripheral interface master

There is provided a method, a system and a device for displaying an image corresponding to a first field of view to an operator of an image capturing device. The method comprises receiving input data relating to a change in at least one of a position, an orientation, or a scaling of the first field of view and determining, based on the input data, at least one of a position, an orientation or a scaling of the first field of view with respect to a second field of view which is larger than the first field of view. Further, the method comprises receiving an image captured by the image capturing device and determining an overlapping portion of the first field of view and the received image. An image to be displayed is then determined by using image data of the received image in the overlapping portion, and using image data of the second field of view in the non-overlapping portion. The invention is advantageous in that it provides an improved operation of the image capturing device.

Control of an image capturing device

The present invention relates to a computer chip having integrated thereon a CPU, and a cache system being interconnected, and at least one synchronization unit. The chip is setable in one of at least two different running modes, a first one thereof being a DUT mode, and a second one thereof being a MONITOR mode. The MONITOR mode is complementary to the DUT mode. The chip additionally comprises a debug bus connectable to another identical chip for communicating signals enabling the chip and said another chip to run in parallel while said chips being in complementary modes. Said signals comprises synchronization signals generated by said synchronization unit. The present invention further relates to a computer apparatus, and a debugging system both employing at least one such chip.

Chip with debug capability

Integrated circuit and method for bringing an integrated circuit to execute instructions

Growing community of inventors

Lund, Sweden

Per Zander