Synopsys, Inc.

Synopsis Incorporated

Per Mattias Bjesse

Himanshu Jain

James Herbert Kukula

Arunava Saha

Pratik Mahajan

Manish Pandey

Carl Preston Pixley

Alfred Koelbl

Sudipta Kundu

Ashvin Mark Dsouza

Sandeep Jana

Systems and techniques are described for using runtime information to identify a verification hole and/or compute a verification metric. Runtime information (RI) for a set of proven assertions can be determined, wherein the RI includes a first set of registers, a first set of inputs, and a first set of constraints that were used by a formal verification engine during runtime to prove one or more assertions for a design under verification (DUV). Next, a second set of registers, a second set of inputs, and a second set of constraints that are not present in the RI can be determined. The second set of registers, the second set of inputs, and/or the second set of constraints can then be used to (1) identify a verification hole and/or (2) compute a verification metric.

Using runtime information from solvers to measure quality of formal verification

The fault analysis problem is modelled by automatically creating additional properties (fault properties) and constraints based on a plurality of injected faults and existing user assertions. These fault properties and constraints are sent to formal verification in a single run to qualify all of the faults together, rather than sequentially checking each fault in a separate formal verification run.

Efficient mechanism of fault qualification using formal verification

Disclosed is a technology for parallelized design verification of two circuit designs at a register transfer level. A plurality of potential equivalent sub-circuit pairs is identified from the circuit designs to create a proof-tree structure. The proof-tree structure includes a root-proof, a plurality of parent-proofs downchain of said root-proof and a plurality of child-proofs downchain of at least one of the parent-proofs. Each one of the child-proofs is associated with a first equivalency status of one of the potential equivalent sub-circuit pairs. The parent-proofs are associated with second equivalency statuses dependent upon the first equivalency statuses of downchain child-proofs. The root-proof is associated with a third functional equivalency status of the two circuit designs dependent upon the second equivalency statuses of downchain parent-proofs. This Abstract is not intended to limit the scope of the claims.

Deep insight for debug using internal equivalence visualization and counter-example for sequential equivalence checking

A formal verification tool that verifies multiple sequentially-generated versions of a core circuit design by obtaining search path information from the formal verification solver for each property that is proven or disproven during a first formal verification session involving an earlier-generated circuit design version, and utilizing the search path information to perform search-path verification processes during a subsequent formal verification session to quickly verify the proven/disproven properties in a later-generated circuit design version. Each property's search path information includes counterexample traces or proof artifacts identifying the search operations utilized to achieve a corresponding counterexample or proof object that proves/disproves the property. Search-path verification involves applying the stored search path information to the later-generated circuit design version, and determining if the same counterexample or proof object is achieved. The stored search path information is also utilized to perform efficient path-influenced search processes when the search-path verification process fails.

Formal verification using cached search path information to verify previously proved/disproved properties

Methods and apparatuses are described for sharing inductive invariants while performing formal verification of a circuit design. Specifically, some embodiments assume at least an inductive invariant for a property to be true while proving another property. According to one definition, an inductive invariant of a property is an inductive assertion such that all states that satisfy the inductive assertion also satisfy the property. According to one definition, an inductive assertion describes a set of states that includes all legal initial states of the circuit design and that is closed under a transition relation that models the circuit design.

Invariant sharing to speed up formal verification

A computer implemented representation of a circuit design is reduced by representing the circuit design as a data structure defining a netlist. A first set of nodes is identified in the netlist that includes datapath nodes, preferably nodes that do not intermingle data and control. The first set of nodes is segmented into segment widths that correspond to uniformly treated segments of the corresponding words. A second set of nodes, including nodes that intermingle data and control, are converted into bit-level nodes. The segmented nodes are analyzed to define reduced safe sizes by applying a computer implemented function. An updated data structure representing the circuit design is then generated using the reduced safe sizes of the segmented nodes.

Method and apparatus for word-level netlist preprocessing and analysis using same

Method and apparatus for word-level netlist reduction and verification using same

Computer implemented techniques for simplification of models are disclosed including various manipulations that are useful in logic analysis, verification, and re-synthesis. A high word-level representation is obtained along with a bit-level design representation. A map between the word-level representation and the bit-level representation is produced. Optimizations are performed on the bit-level representation with the results being lifted and included in the word-level representation, based on the map. Similar optimizations are performed on the word-level representation and translated to the bit-level representation.

Bit-level simplification of word-level models

A computer implemented representation of a circuit design including memory is abstracted to a smaller netlist by replacing memory with substitute nodes representing selected slots in the memory, segmenting word level nodes, including one or more of the substitute nodes, in the netlist into segmented nodes, finding reduced safe sizes for the segmented nodes and generating an updated data structure representing the circuit design using the reduced safe sizes of the segmented nodes. The correctness of such systems can require reasoning about a much smaller number of memory entries and using nodes having smaller bit widths than exist in the circuit design. As a result, the computational complexity of the verification problem is substantially reduced.

Method and apparatus for memory abstraction and for word level net list reduction and verification using same

A computer implemented representation of a circuit design including memory is abstracted to a smaller netlist, which can be analyzed by standard verification tools and by other tools that operate on netlists. The correctness of such systems can require reasoning about a much smaller number of memory entries than exist in the circuit design, and by abstracting such memories to a smaller number of entries, the computational complexity of the verification problem is substantially reduced.

Method and apparatus for memory abstraction and verification using same

A method for functional verification includes transforming an original multiphase circuit design into a phase-abstracted circuit design by identifying cyclical (repetitive) signals in the multiphase circuit design, determining a number of simulation phases for the multiphase circuit design, unwinding the multiphase circuit design by the number of phases to create an unwound design, and then applying logic reduction techniques to the unwound design using the clock-like signals to reduce (simplify) the logic in the unwound design by eliminating unused/unnecessary registers, inputs, outputs, and logic. The resulting phase-abstracted design can then be processed much more efficiently by functional verification engines than the original multiphase circuit design due to the reduced number of registers/inputs.

Growing community of inventors

Portland, OR, United States of America

Per Mattias Bjesse