Telefonaktiebolaget Lm Ericsson (publ)

St-ericsson Sa

Per-Inge Tallberg

Ulf Morland

Harald Gustafsson

Jonas Bengtsson

Andreas Anyuru

Staffan Månsson

Dan Korsfeldt

Dejan Miljkovic

Johan Svensson

Karol Krakowiak

Jens Kongstad

Peter Nessrup

Rickard Andersson

Milica Bogdanovic

Niklas Larsson

Karl Komierowski

A scheduler and method for scheduling data transmission in a wireless communication system are disclosed. The scheduler buffers data packets in a buffer and monitors status of the buffer. The buffered data packets will remain in the buffer, until the buffer contains a data packet which is associated with a priority level higher than a priority level of a predefined priority threshold. Then, the scheduler selects a modulation and coding scheme for the buffered data packets and sends the buffered data packets to a radio unit for transmission.

Scheduler and methods therein for scheduling data transmission in a wireless communication system

A computing device includes at least one master unit; at least one slave unit; an interconnect structure configured to route transactions from the at least one master unit to the at least one slave unit; and a transaction logger device configured to intercept and save a record of outstanding transactions sent by the at least one master unit to the interconnect structure. The transaction logger device is further configured to preserve the record of outstanding transactions when at least a part of the computing device is restarted.

Method, system and architecture for bus transaction logger

Methods of operation and interrupt controllers for generating interrupt signals to a unit, which could enter an active mode and a non-active mode, are disclosed. The interrupt controllers have interrupt logic () adapted for receiving requests for interrupt, activity mode logic () adapted for receiving information whether the unit is in non-active mode, and delay control logic () adapted for delaying the interrupt to the unit when the received information indicates that the unit is in non-active mode.

Interrupt controller and methods of operation

A hardware device register is written without transferring the register content from the hardware device to a host device over an interface bus for modification. The hardware device receives an address identifying the target register included in the hardware device and bit information associated with a write operation involving the target register from the host device over the interface bus. The address is stored in a first register included in the hardware device and dedicated for supporting write operations. The bit information is stored in a second register included in the hardware device and also dedicated for supporting write operations. The target register is accessed based on the address stored in the first register dedicated for supporting write operations and one or more bits of the target register are written based on the bit information without first transferring the register content to the host device over the interface bus.

Masked register write method and apparatus

Growing community of inventors

Lund, Sweden

Per-Inge Tallberg