Intel Corporation

Per H Hammarlund

Hong Wang

Stephan Jourdan

Gautham N Chinya

John Thomas Shen

Perry H Wang

John P Shen

Xiang Chris Zou

Bryant E Bigbee

Shivnandan D Kaushik

Scott Dion Rodgers

Xinmin Tian

Glenn J Hinton

Avinash Sodani

Richard A Hankins

Baiju V Patel

Prashant Sethi

James Paul Held

Gad Shlomo Sheaffer

Matthew C Merten

Anil Aggarwal

Alexandre J Farcy

Sebastien Hily

Steve Shih-wei Liao

Milind Baburao Girkar

Bratin Saha

Quinn Able Jacobson

Robert F Krick

James B Crossland

Alan Beecher Kyker

Ronak Singhal

Douglas M Carmean

Chan W Lee

Hitesh Ahuja

Piyush N Desai

Joseph F Rohlman

Tor M Aamodt

William Alexander

Martin Guy Dixon

Michael Cornaby

Kshitij Arun Doshi

Vivek K De

Hong Jiang

Stephen H Gunther

David J Sager

Dion Rodgers

Darrell D Boggs

Asit K Mallick

Belliappa Manavattira Kuttanna

Doron Orenstein

Herbert H J Hum

Yuval Yosef

Ethan Schuchman

Suresh Srinivas

Hermann Gartler

Shiv Kaushik

Taraneh Bahrami

Edward Thomas Grochowski

Ali-Reza Adl-Tabatabai

Francis X Mckeen

Arvind A Kumar

Ittai Anati

Michael A Fetterman

George Zacharias Chrysos

Mark C Davis

Chris J Newburn

Jamison D Collins

Michael D Upton

Jared Warner Stark, Iv

Pedro Marcuello

Gerolf F Hoflehner

John Alan Miller

Johan G Van De Groenendaal

Ed Grochowski

Thiam Wah Loh

Aravindh Baktha

Jason W Brandt

Robert J Greiner

Yen-Kuang Chen

William W Macy, Jr

Herbert H Hum

David A Koufaty

Antonio Gonzalez

Robert Geva

Thomas R Huff

Matthew J Holliman

Antonio González

Stephen J Robinson

Sanjiv M Shah

John L Reid

Ryan N Rakvic

Robert P Knight

James Charles Abel

Deepak A Mathaikutty

Larry O Smith

David K Poulsen

Zhongying Zhang

Morris Marden

Robert L Hinton

Ali-Reza Adi-Tabatabai

Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.

Programmable event driven yield mechanism which may activate other threads

In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

Mechanism for instruction set based thread execution on a plurality of instruction sequencers

A processor is disclosed and includes at least one core including a first core, and interrupt delay logic. The interrupt delay logic is to receive a first interrupt at a first time and delay the first interrupt from being processed by a first time delay that begins at the first time, unless the first interrupt is pending at a second time when a second interrupt is processed by the first core. If the first interrupt is pending at the second time, the interrupt delay logic is to indicate to the first core to begin to process the first interrupt prior to completion of the first time delay. Other embodiments are disclosed and claimed.

Synchronization of interrupt processing to reduce power consumption

Mechanism for instruction set based thread execution of a plurality of instruction sequencers

Systems and methods for employing hardware-assisted virtualization for implementing a secure video output path. An example processing system comprises: a memory; a shared interconnect; and a processing core communicatively coupled to the memory via the shared interconnect, the processing core to: initialize a first virtual machine and a second virtual machine; responsive to receiving a memory access transaction initiated by the first virtual machine to access a memory buffer, tag the memory access transaction with an identifier of the first virtual machine; and responsive to receiving a digital content decoder access transaction initiated by the second virtual machine, tag the digital decoder access transaction with an identifier of the second virtual machine.

Hardware-assisted virtualization for implementing secure video output path

A method, apparatus, and system are provided for performing compare and exchange operations using a sleep-wakeup mechanism. According to one embodiment, an instruction at a processor is executed to help acquire a lock on behalf of the processor. If the lock is unavailable to be acquired by the processor, the instruction is put to sleep until an event has occurred.

Compare and exchange operation using sleep-wakeup mechanism

Methods and apparatuses for reducing power consumption of processor switch operations are disclosed. One or more embodiments may comprise specifying a subset of registers or state storage elements to be involved in a register or state storage operation, performing the register or state storage operation, and performing a switch operation. The embodiments may minimize the number of registers or state storage elements involved with the standby operation by specifying only the subset of registers or state storage elements, which may involve considerably fewer than the total number of registers or state storage or elements of the processor. The switch operation may be switch from one mode to another, such as a transition to or from a sleep mode, a context switch, or the execution of various types of instructions.

Single instruction for specifying a subset of registers to save prior to entering low-power mode, and for specifying a pointer to a function executed after exiting low-power mode

In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.

Instruction set architecture-based inter-sequencer communications with a heterogeneous resource

Single instruction for specifying and saving a subset of registers, specifying a pointer to a work-monitoring function to be executed after waking, and entering a low-power mode

In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed.

Instruction for enabling a processor wait state

Growing community of inventors

Hillsboro, OR, United States of America

Per H Hammarlund