Thin Film Electronics Asa

Other

Opticom Asa

Patinor As

Dyno Particles A.s.

Per-Erik Nordal

Hans Gude Gudesen

Geirr Ivarsson Leistad

Johan Carlsson

Mats Johansson

Göran Gustafsson

Michael O Thompson

Christer Karlsson

Thomas W Ebbesen

Per Bröms

Per Hamberg

G&ouml;ran Gustafsson

Per Sandström

Nicklas Ojakangas

Rolf Magnus Berggren

Mats Sandberg

Johan Roger Axel Karlsson

Thormod Nae Buttedringsrud

Grzegorz Greczynski

Rolv Mo Nilsen

Geirr Ivarsson Leidstad

Reidar E Tangen

Per Br&ouml;ms

Bengt G&ouml;ran Gustafsson

Rolf Magnue Berggren

Terje Skotheim

Per Carlsen

Svein O Kanstad

Linda Andersson

Goran Gustafsson

Bengt Goran Gustafsson

Johan Roger Karlsson

A solution mined cavity system and method are disclosed. The system comprises an underground cavity created by solution mining in salt deposits, an upper water reservoir, tubing structure adapted to lead water from the upper water reservoir into the underground cavity and out of the underground cavity, and a pumping device adapted to contribute to pumping water from the upper water reservoir via the tubing structure out of the cavity.

Solution mined cavity system

An underwater energy storage system comprising a container where energy is stored by transporting water between the container and a body of water, is disclosed.The container comprises a water- and gas-tight membrane surrounding a container volume, where the container is rendered mainly incompressible by a fill material comprising densely packed, incompressible objects arranged in the container volume, the fill material forming a mainly incompressible aggregate.

Underwater energy storage system

In a method for obviating the effect of disturb voltages in a data storage apparatus employing passive matrix addressing, an application of electric potentials for an addressing operation is according to a voltage pulse protocol. The data storage cells of the apparatus are provided in two or more electrically separated segments each constituting non-overlapping physical address subspaces of the data storage apparatus physical address space. A number of data storage cells in each segment are preset to the same polarization by an active voltage pulse with a specific polarization. In a first addressing operation one or more data storage cells are read by applying an active pulse with the same polarization to each data storage cell and recording the output charge response. On basis thereof the output data in subsequent second addressing operation are copied onto preset data storage cells in another segment of the data storage apparatus, this segment being selected on the basis of its previous addressing history.

Method for operating a data storage apparatus employing passive matrix addressing

In a method for reducing detrimental phenomena related to disturb voltages in a data storage apparatus employing passive matrix addressing, particularly a memory device or a sensor device, an application of electric potentials conforming to an addressing operation is generally controlled in a time-coordinated manner according to a voltage pulse protocol. In an addressing operation a data storage cell is set to a first polarization state by means of a first active voltage pulse and then, dependent on the voltage pulse protocol, a second voltage pulse which may be a second active voltage pulse of opposite polarity to that of the first voltage pulse, is applied and used for switching the data storage cell to a second polarization state. The addressed cell is thus set to a predetermined polarization state as specified by the addressing operation. The data storage cells of the apparatus are provided in two or more electrically separated segments such that each segment comprises a separate physical address space for the apparatus. In an addressing operation the data are directed to a segment that is selected based on information on prior and/or scheduled applications of active voltage pulses to the segments.

An organic electronic device consists of one or more electro-active organic or polymer materials sandwiched between electrodes. Critical in such devices is the interface between the electrode and the polymer, where degradation or chemical reaction products may develop that are deleterious to the proper functioning of the device. This is solved by introducing a functional interlayer composed of one or more materials consisting of a molecular backbone bearing phosphonate or phosphate functions, either directly attached or through side chains, said functional layer being disposed between at least one of the respective electrodes and said one or more electro-active materials in the device.

Organic electronic device and methods for manufacturing a device of this kind

An apparatus/method for producing fabric-like electronic circuit patterns created by methodically joining electronic elements using textile fabrication-like methods in a predetermined arrangement.

Apparatus comprising electronic and/or optoelectronic circuitry and method for realizing said circuitry

In a heating and temperature control system for a data storage apparatus comprising at least one matrix-addressable ferroelectric or electret memory device, Joule heating means are provided in the memory device, a temperature determining means is connected with controller circuitry and the controller circuitry is connected with an external power supply, which controlled by the former powers the Joule heating means to achieve a selected operating temperature. In a method for operating the heating and temperature control system an ambient or instant temperature of the memory device is determined and compared with the set nominal optimal temperature, and the difference between these temperatures is used in a predefined algorithm for establishing control parameters for the application of power to the Joule heating means to achieve the selected operating temperature in the memory device during an addressing operation thereto.

Operating temperature optimization in a ferroelectric or electret memory

In a method for operating a passive matrix-addressable ferroelectric or electret memory device, a voltage pulse protocol based on a 1/3 voltage selection rule is used in order to keep disturb voltages at minimum, the voltage pulse protocol comprising cycles for read and write/erase bases on time sequence of voltage pulses with defined parameters. The method comprises a refresh procedure wherein cells for refresh are selected and refresh requests processed by a memory device controller, the refresh requests are monitored and processed in regard of ongoing or scheduled memory operations, and refresh voltage pulses with defined parameters are applied to the memory cells selected for refresh, while simultaneously ensuring that non-selected memory cells are subjected to zero voltage or voltages which do not affect the polarization state of these cells.

Method for operating a passive matrix-addressable ferroelectric or electret memory device

In a memory and/or data processing device having at least two stacked layers which are supported by a substrate or forming a sandwiched self-supporting structure, wherein the layers include memory and/or processing circuitry with mutual connections between the layers and/or to circuitry in the substrate, the layers the are mutually arranged such that contiguous layers form a staggered structure on at least one edge of the device and at least one electrical edge conductor is provided passing over the edge on one layer and down one step at a time, enabling the connection to an electrical conductor in any of the following layers in the stack. A method for manufacturing a device of this kind includes the steps for adding the layers successively, one layer at a time, such that the layers form a staggered structure, and for providing one or more layers with at least one electrical contact pad for linking to one or more interlayer edge connectors.

Vertical electrical interconnections in a stack

In a ferroelectret or electret memory cell a polymeric memory material is a blend of two or more polymeric materials, the polymeric material being provided contacting first and second electrodes. Each electrode is a composite multilayer having a first highly conducting layer and a conducting polymer layer, the latter forming a contact between the former and the memory material.

Memory cell

A method of driving a passive matrix display or memory array of cells comprising an electrically polarizable material exhibiting hysteresis, in particular a ferroelectric material, wherein the polarization state of individual cells can be switched by application of electric potentials or voltages to word and bit lines in the matrix or array.

Addressing of memory matrix

A matrix-addressable ferroelectric or electret memory device and a method of operating are explained. The method includes applying a first plurality of voltage difference across a first and a second set of electrodes in the memory when data are read, and applying a second plurality of voltage differences when data are refreshed or rewritten. The first and second plurality of voltage differences correspond to sets of potential levels comprising time sequences of voltage pulses. At least one parameter indicative of a change in a memory cell response is used for determining at least one correction factor for the voltage pulses, whereby the pulse parameter is adjusted accordingly. The memory device comprises means for determining the at least one parameter, a calibration memory connected with means for determining the correction factor, and control circuits for adjusting pulse parameters as applied to read and write operations in the memory device.

Method for operating a ferroelectric of electret memory device, and a device of this kind

In a method for determining the logic state of memory cells in a passive matrix-addressable data storage device with word and bit lines, components of current response are detected and correlated with a probing voltage, and a time-dependent potential is applied on selected word and bit lines or groups thereof, said potentials being mutually coordinated in magnitude and time such that the resulting voltages across all or some of the non-addressed cells at the crossing points between inactive word lines and active bit lines are brought to contain only negligible voltage components that are temporally correlated with the probing voltage. A first apparatus according to the invention for performing the method provides sequential readout of all memory cells on an active word line (AWL) by means of detection circuits (). An active word line (AWL) is selected by a multiplexer (), while inactive word lines (IWL) are clamped to ground during readout. A second apparatus for performing the method is rather similar, but has only a single detection circuit (). An active word line (AWL) is selected by multiplexer () and a bit line (ABL) is selected by a multiplexer () provided between one end of the bit lines (BL) and the input of the detection circuit (), while inactive word and bit lines (IWL; IBL) are clamped to ground during readout.

Non-destructive readout

A scaleable integrated data processing device, particularly a microcomputer, comprises a processing unit with one or more processors and a storage unit with one or more memories. The data processing device is provided on a carrier substrate (S) and comprises mutually adjacent substantially parallel layers (P, M, MP) stacked up on each other, the processing unit and the storage unit being provided in one or more such layers and the separate layers formed with a selected number of processors and memories in selected combinations. In each layer are provided horizontal electrical conducting structures which constitute electrical internal connections in the layer and besides each layer comprises further electrical conducting structures which provide electrical connections to other layers and to the exterior of the data processing device. The integrated data processing device has a scaleable architecture, such that it in principle can be configured with an almost unlimited processor and memory capacity. Particularly can the data processing device implement various forms of scaleable parallel architectures integrated with optimal interconnectivity in three dimensions.

Scaleable integrated data processing device

A ferroelectric or electret memory circuit, particularly a ferroelectric or electret memory circuit with improved fatigue resistance, including a ferroelectric or electret memory cell with a polymer or oligomer memory material contacting first and second electrodes, at least one of the electrodes is comprised of at least one functional material capable of physical and/or chemical bulk incorporation of atomic or molecular species contained in either the electrode or the memory material and displaying a propensity for migrating in the form of mobile charged and/or neutral particles between an electrode and a memory material, something which can be detrimental to both. A functional material with the above-mentioned properties shall serve to offset any adverse effect of a migration of this kind, leading to an improvement in the fatigue resistance of the memory cell. The memory circuit being used in a matrix-addressable memory device where the memory cells are formed in distinct portions in a global layer of a ferroelectric or electret thin-film memory material, particularly a polymer material.

Growing community of inventors

Asker, Norway

Per-Erik Nordal