Thin Film Electronics Asa

Xerox Corporation

Per Bröms

Christer Karlsson

Hans Gude Gudesen

Geirr Ivarsson Leistad

Jakob Nilsson

Olle Jonny Hagel

Per-Erik Nordal

Mats Johansson

Göran Gustafsson

Johan Carlsson

Per Hamberg

Staffan Björklid

Per Sandström

Hamberg Per

A ferroelectric memory cell () and a memory device () comprising one or more such cells (). The ferroelectric memory cell comprises a stack () of layers arranged on a flexible substrate (). Said stack comprises an electrically active part () and a protective layer () for protecting the electrically active part against scratches and abrasion. Said electrically active part comprises a bottom electrode layer () and a top electrode layer () and at least one ferroelectric memory material layer () between said electrodes. The stack further comprises a buffer layer () arranged between the top electrode layer () and the protective layer (). The buffer layer () is adapted for at least partially absorbing a lateral dimensional change (&#x394;L) occurring in the protective layer () and thus preventing said dimensional change (&#x394;L) from being transferred to the electrically active part (), thereby reducing the risk of short circuit to occur between the electrodes.

Short circuit reduction in a ferroelectric memory cell comprising a stack of layers arranged on a flexible substrate

An electronic component () and an electronic device () comprising one or more such components (). The electronic component () comprises a stack () of layers arranged on a flexible substrate (). Said stack comprises an electrically active part () and a protective layer () for protecting the electrically active part against scratches and abrasion. Said electrically active part comprises a bottom electrode layer () and a top electrode layer () and at least one insulating or semi-insulating layer () between said electrodes. The stack further comprises a buffer layer (), arranged between the top electrode layer () and the protective layer (). The buffer layer () is adapted for at least partially absorbing a lateral dimensional change (&#x394;L) occurring in the protective layer () and thus preventing said dimensional change (&#x394;L) from being transferred to the electrically active part (), thereby reducing the risk of short circuit to occur between the electrodes.

Short circuit reduction in an electronic component comprising a stack of layers arranged on a flexible substrate

In a non-volatile electric memory system a memory unit and a read/write unit are provided as physically separate units. The memory unit is based on a memory material that can be set to at least two distinct physical states by applying an electric field across the memory material. Electrodes and/or contacts are either provided in the memory unit or in the read/write unit and contacts are at least always provided in the read/write unit. Electrodes and contacts are provided in a geometrical arrangement, which defines geometrically one or more memory cells in the memory layer. Establishing a physical contact between the memory unit and the read/write unit closes an electrical circuit over the addressed memory cell such that read, write or erase operations can be effected. The memory material of the memory unit can be polarized into two discernible polarization states.

Card-like memory unit with separate read/write unit

In a heating and temperature control system for a data storage apparatus comprising at least one matrix-addressable ferroelectric or electret memory device, Joule heating means are provided in the memory device, a temperature determining means is connected with controller circuitry and the controller circuitry is connected with an external power supply, which controlled by the former powers the Joule heating means to achieve a selected operating temperature. In a method for operating the heating and temperature control system an ambient or instant temperature of the memory device is determined and compared with the set nominal optimal temperature, and the difference between these temperatures is used in a predefined algorithm for establishing control parameters for the application of power to the Joule heating means to achieve the selected operating temperature in the memory device during an addressing operation thereto.

Operating temperature optimization in a ferroelectric or electret memory

A passive matrix-addressable device may include individually addressable cells of a polarizable material. The cells store data in one of two polarization states in each cell, and the polarization states in the cells are written and read by addressing via electrodes which form word and bit lines. The cells are provided in or at the crossings between the word and bit lines and a voltage pulse protocol is used read and write data to cells. During reading, a word line is activated by applying voltage which relative to the potential on all crossing bit lines corresponds to the voltage Vand data stored in the cells connected to this active word line are determined by detecting the charge values of the cells.

Method for reading a passive matrix-addressable device and a device for performing the method

A matrix-addressable ferroelectric or electret memory device and a method of operating are explained. The method includes applying a first plurality of voltage difference across a first and a second set of electrodes in the memory when data are read, and applying a second plurality of voltage differences when data are refreshed or rewritten. The first and second plurality of voltage differences correspond to sets of potential levels comprising time sequences of voltage pulses. At least one parameter indicative of a change in a memory cell response is used for determining at least one correction factor for the voltage pulses, whereby the pulse parameter is adjusted accordingly. The memory device comprises means for determining the at least one parameter, a calibration memory connected with means for determining the correction factor, and control circuits for adjusting pulse parameters as applied to read and write operations in the memory device.

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Linköping, Sweden

Per Bröms