Cadence Design Systems, Inc.

Per Anders M Franzen

Ziyad Hanna

Habeeb Farah

Rajeev Kumar Ranjan

Ross M Weber

A computer-implemented method and non-transitory computer readable medium for circuit design verification. Formal verification is performed on a circuit design to prove a correctness of a property of the circuit design. The circuit design has a cone of influence representing a portion of the circuit design capable of affecting signals of the property. A proof core of the circuit design is identified, the proof core being a portion of the cone of influence that is sufficient to prove the correctness of the property. A coverage metric is generated that is indicative of a level of formal verification coverage provided by the property based on the proof core of the circuit design.

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Gothenburg, Sweden

Per Anders M Franzen