Telefonaktiebolaget Lm Ericsson (publ)

Sony Ericsson Mobile Communications Ab

Other

Per Anders Holmberg

Henrik Bengtsson

Lars Eriksson

Leif Johansson

Tomas Lars Jonsson

Lars Manholm

Lars-Örjan Kling

Terje Egeland

Dan Olov Halvarsson

Nils Ola Linnermark

Lars Winberg

Bengt Inge Svensson

Henrik Heringslack

Mats Ove Larsson

Ulf Eric Andretzky

Lars-&Ouml;rjan Kling

G&ouml;ran Snygg

Sten E Johnson

Fredrik Bagenholm

Magnus Carlsson

Stefan Sorensson

G&ouml;ran Engblom

Tommy Sandevi

Håkan Bygdö

Eyvind Frilund

Onar Olsen

Daniel Friman

Lennart Michael Rosendahl

Mats Holmberg

Michael Rosendahl

Kristian Lassesson

Nikhil Tikekar

Karl Oscar Joachim Str&ouml;mbergson

Emil Wikgren

Peter Norrman

Anders Widell

Fredrik Strandberg

Tomas Ericsson

Marcus Dahlström

Sten Edward Johnson

M Indian Inst Of Tech Powai Sohoni

Hakan Bygdö

Dan Olov Halvorsson

Ulf Erik Andretzky

Karl Oscar Joachim Strömbergson

A method is implemented by a computing device for atomic multicast support for a multicast group, includes receiving a message order from a sequencer via remote write, the message order defining a sequence for a plurality of messages from a multicast group, receiving the plurality of messages from at least one sender in the multicast group via remote write, and providing the plurality of messages to an application in the message order, in response to determining that all of the plurality of messages have been received.

Ultra-low latency atomic multicast

A method implemented by an electronic device for sending data on low latency communication includes remote writing a sequence number of a message to be sent next to a receiver, determining whether there is an open position in a receive buffer of the receiver using a local tracking mechanism, writing data of the message to an area of an address space of a sending application that is mapped onto the receive buffer as a result of determining there is the open position in the receive buffer, incrementing a local sequence counter, and updating position information in the local tracking mechanism.

Low latency small message communication channel using remote write

A processing system has at least one internal processing unit and associated memory. The memory is accessible by at least two other independent processing units, and the memory of the at least one internal processing unit includes a data structure shared by the at least two other independent processing units that are allowed to perform direct memory writes into the shared data structure. A dedicated set of one or more bits in the shared data structure is allocated to each one of the at least two other independent processing units, each bit or each group of bits in the shared data structure indicates a unique combination of independent processing unit and application handler for handling an application in relation to the corresponding independent processing unit. Preparation and/or activation of the application handler indicated by the set bit or the set group of bits is initiated.

Bit register in shared memory indicating the processor and the software handlers

There is provided a radio access network node () for a wireless communication system, wherein the radio access network node () is configured to be implemented as a clustered system comprising a cluster of interconnected network node sub-modules (). Each network node sub-module () comprises a processing unit () and memory (), and the memory () comprises a data structure. At least one of the network node sub-modules () is configured to manage at least one radio and/or antenna unit (). The radio access network node () also has a communication mechanism for communication between the network node sub-modules (), and the communication mechanism is configured to enable a direct memory write operation from at least one network node sub-module into the data structure of at least one other network node sub-module.

Radio access network node technology

There is provided a method and system () for power management of an event-based processing system (). The system () is configured to obtain information representing a history of arrival times of events, wherein the information comprises arrival timestamps of the events. The system () is configured to determine a measure for power management based on the timestamps of at least two events represented in the information. The system () is also configured to perform power management based on the determined measure.

Power management of an event-based processing system

A method, load regulator, and profiling tool for monitoring and analyzing system performance and spare CPU capacity in a system such as a telecommunication system. The load regulator and profiling tool utilize a communication interface to balance the profiling performance of the profiling tool with the available spare CPU capacity in the system. The load regulator regularly sends information to the profiling tool of any spare CPU capacity during profiling, and the profiling tool adjusts the profiling performance gradually in response to the received information.

Load balanced profiling

The invention relates to a data input interface arranged to input data comprising a first set of keys, wherein all or a majority of the keys is adapted to indicate an input of a first set of symbols, arranged in a first structure, and a second set of keys, wherein all or a majority of the keys is adapted to indicate an input of a second set of symbols, arranged in a second structure, wherein the first set of keys and the second set of keys are integrated with each other.

Data input interface and method for inputting data

A device may include logic configured to process a request for a keypad layout, and to provide a keypad layout via keypad display in response to the processed request.

Programmable keypad

The present invention relates to mechanisms for handling and detecting collisions between threads () that execute computer program instructions out of program order. According to an embodiment of the present invention each of a plurality of threads () are associated with a respective data structure () comprising a number of bits () that correspond to memory elements (m, m, m, m) of a shared memory (). When a thread accesses a memory element in the shared memory, it sets a bit in its associated data structure, which bit corresponds to the accessed memory element. This indicates that the memory element has been accessed by the thread. Collision detection may be carried out after the thread has finished executing by means of comparing the data structure of the thread with the data structures of other threads on which the thread may depend.

Collision handling apparatus and method

An electronic device is provided that includes a main printed circuit board (PCB) having a top surface, a bottom surface, and a hole extending between the top surface and the bottom surface. The electronic device further includes a module PCB having at least one electrical component mounted on a top surface of the module PCB, wherein the module PCB is inverted and assembled adjacent the main PCB such that the top surface of the module PCB faces the top surface of the main PCB, and the at least one electrical component extends into the hole. In addition, the electronic device includes a cover on the bottom surface of the main PCB that substantially covers the hole.

Electronic device with flip module having low height

A shielding device configured to provide EMI or ESD protection to an electronic component () comprises a cover (), and a wall () of a resilient material. By molding the resilient material under the influence of a magnetic field provided by a number of separate magnets, a dispersed plurality of magnetically attractable particles in the material are concentrated in strings () extending between a lower () and upper () end of the wall. The cover is attached to connect to the strings affixed in the solidified wall at the upper end of the wall, and at the lower end of the wall the strings are placed in contact with a ground trace () formed around the component to be shielded, thereby forming a Faraday cage about the component.

Method of making a shielding device

The invention relates to a cover for a portable device () comprising: a main body () with resilient parts, an opening () provided in a resilient part () for insertion and removal of the portable device (); and a releasable cap () shaped and configured to close the opening () and fit over at least a part of the resilient part () surrounding the opening ().

Cover for portable device

A cover for a portable device comprising: a main body, an opening provided in a resilient part () of the main body for insertion and removal of the portable device, wherein the opening is provided at one side, and with a shape comprising an upper lip () and a lower lip () extending along the whole width, and rounded corners being retracted along the longitudinal direction of the cover behind the front of the upper lip () and the front of the lower lip ().

A cover for a portable device comprising; a main body () with resilient parts, an opening provided in a resilient part () for insertion and removal of the portable device in an insertion/removal direction, wherein the main body is provided with a number of elements projecting on the inside, extending in parallel with the insertion/removal direction.

The read latency caused by job start preparation of a future job is at least partly hidden within the current job by reading information for job start preparation of the future job integrated with the execution of the current job. Instructions for job start preparation are preferably instrumented () into the current job and executed (), whenever possible, in parallel with the instructions of the current job. The integrated job start preparation may include table look-ups, register file updating, instruction fetching and preparation. If the scheduled job order is allowed to change during execution, it is typically necessary to test () whether the next job is still valid before starting the execution, it is typically necessary to test () whether the next job is still valid before starting the execution of the next job and take appropriate actions () depending on the outcome of the test. In addition to reduced job start preparation time, unused slots in the instruction-parallel execution of the current job may be filled up by the added read instructions, thus providing more efficient utilization of the multiple functional execution units of the processor.

Hidden job start preparation in an instruction-parallel processor system

Growing community of inventors

Stockholm, Sweden

Per Anders Holmberg