Stmicroelectronics (beijing) R&d Company Ltd.

Stmicroelectronics S.r.l.

Beijing Research Institute of Uranium Geology

Stmicroelectronics (bejing) R&d Company Ltd.

PengFei Zhu

HongXia Sun

Elio Guidetti

Xiao Kang Jiao

YongQiang Wu

Bo Peng

Qiang Guo

Shan Jiang

Yunlong Zhang

Feng He

Mingkuan Qin

Hu Liu

Yongqiang Wu

Xinyang Liu

Zilong Zhang

Jun Zhong

Kai Wang

Ziying Li

Chiheng Liu

Qubo Wu

Weitao Li

Yuyan Zhang

Licheng Jia

Wusheng Liu

Ye Sun

Ruixiang Hao

Yuqi Cai

Xiaoqian Xiu

Xide Li

Gui Wang

Jielin Zhang

Meizhi Han

Jianfang Cai

Qingyin Guo

Shengfu Li

Zhongbo He

Junxian Wang

Linfei Qiu

Jinrong Lin

Wenquan Wang

Xiaoneng Luo

Mingming Tian

Changfa Yu

Longsheng Yi

Guo Wang

Jian Guo

Hongwei Ji

Sheng He

Zhixin Huang

The present disclosure relates to a method for analyzing a geological body with the help of physical and chemical properties thereof, and in particular, to a method for identifying an exudative sandstone uranium deposit. With the method for identifying an exudative sandstone uranium deposit according to the embodiments of the present disclosure, an exudative sandstone uranium deposit formed by an exudation metallogenesis may be systematically identified, so as to guide prediction and prospecting evaluation of a uranium deposit in red variegated sandstone formations of a sedimentary basin, avoid ore dislocation and ore leakage, open up new prospecting positions and spaces, and break through new uranium resources.

Method for identifying exudative sandstone uranium deposit

A debug-enabled processing device includes a processor, a communication transceiver circuit, and a debug support unit. The debug support unit has a plurality of dedicated debug registers to facilitate debugging a software program under execution by the processor. One of the plurality of debug registers is a control register having at least four bits, which are used to enable/disable a plurality of debugging operations. Others of the debug registers include a set of index registers that may be configured to pass data to and from the processor.

Debugging support unit for microprocessor

A decoding logic method is arranged to execute a zero-overhead loop in an embedded digital signal processor (DSP). In the method, instruction data is fetched from a memory, and a plurality of instruction tokens, which are derived from the instruction data, are stored in a token buffer. A first portion of one or more instruction tokens from the token buffer are passed to a first decode module, which may be an instruction decode module, and a second portion of the one or more instruction tokens from the token buffer are passed to a second decode module, which may be a loop decode module. The second decode module detects a special loop instruction token, and based on the detection of the special loop instruction token, a loop counter is conditionally tested. Using the first decode module, at least one instruction token of an iterative algorithm is assembled into a single instruction, which is executable in a single execution cycle. Based on the conditional test of the loop counter, the first decode module further assembles a loop branch instruction of the iterative algorithm into the single instruction executable in one execution cycle.

Zero-overhead loop in an embedded digital signal processor

Apparatus and method for a modified, balanced throughput data-path architecture is given for efficiently implementing the digital signal processing algorithms of filtering, convolution and correlation in computer hardware, in which both data and coefficient buffers can be implemented as sliding windows. This architecture uses a multiplexer and a data path branch from the Address Generator unit to the multiply-accumulate execution unit. By selecting between the data path of Address Generator to execution unit and the data path of register to execution unit, the unbalanced throughput and multiply-accumulate bubble cycles caused by misaligned addressing on coefficients can be overcome. The modified balanced throughput data-path architecture can achieve a high multiply-accumulate operation rate per cycle in implementing digital signal processing algorithms.

Modified balanced throughput data-path architecture for special correlation applications

An apparatus and method are disclosed to implement digital signal processing operations involving multiply-accumulate (MAC) operations, by using a modified balanced data structure and accessing architecture. This architecture maintains a data-path connecting one address generation unit, one register file and one MAC execution unit. The register file has a hierarchical grouping organization of individual registers, which reduces bubble cycles caused by memory misalignments. This architecture uses parallel execution and can achieve two or more MAC operations per cycle.

Data accessing method to boost performance of FIR operation on balanced throughput data-path architecture

A register file organization is used to support multiple accesses from more than one processor or pipeline. This shared register file is organized for a multiple processor device that includes a high performance (HP) and a low power (LP) core. The shared register file includes separate HP and LP storage units coupled to separate HP and LP write and read ports.

Register file organization to share process context for heterogeneous multiple processors or joint processor

In mesh networks having multiple nodes that communicate data to and from each other, a great number of data transmissions may be initiated and carried out to get data to a proper processing node for execution. To get data where it needs to go (e.g., the proper destination node), a routing algorithm is used to define a set of rules for efficiently passing data from node to node until the destination node is reached. For the purpose of assuring that all data is properly transferred from node to node in a reasonably efficient manner, a routing algorithm may define subsets of nodes into regions and then send data via the regions. Even greater overall efficiency may be realized by recognizing specific adjacency relationships among a group of destination nodes and taking advantage of such adjacencies by rerouting data through regions other than the region in which a destination node resides.

Modified tree-based multicast routing schema

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Beijing, China

PengFei Zhu