Globalfoundries Singapore Pte. Ltd.

United Microelectronics Corp.

Pengfei Guo

Shyue Seng Tan

Yu-Cheng Tung

Danny Pak-Chum Shum

Zhibiao Zhou

Guowei Zhang

Shao-Hui Wu

Francis YongWee Poh

Hai Biao Yao

Yuanli Ding

A semiconductor device includes a substrate, a source region and a drain region, a gate dielectric layer, and a ferroelectric material layer. The ferroelectric material layer overlaps with the source region and overlaps with the drain region. The substrate further comprises a channel layer. A gate electrode is disposed on the substrate. The ferroelectric material layer is disposed between the channel layer and the gate electrode.

Semiconductor device having a ferroelectric material layer

Device and methods for forming a single transistor non-volatile (NV) multi-time programmable (MTP) memory cell are disclosed. The disclosed memory cell is derived via the disclosed method that includes providing a substrate and forming at least a transistor well with a second polarity type dopant and first and second capacitor wells with a first polarity type dopant in the substrate. The method also includes forming a transistor having a floating gate over the transistor well, a control gate over the first capacitor well and coupled to the floating gate, an erase gate over the second capacitor well and coupled to the floating gate. The control gate comprises a control capacitor while the erase gate comprises an erase capacitor that is decoupled from the control capacitor.

Cost-free MTP memory structure with reduced terminal voltages

Multi-time programmable (MTP) memory cells, integrated circuits including MTP memory cells, and methods for fabricating MTP memory cells are provided. In an embodiment, an MTP memory cell includes a semiconductor substrate, a p-well formed in the semiconductor substrate, and an n-well formed in the semiconductor substrate and isolated from the p-well. The MTP memory cell further includes a p-channel transistor disposed over the n-well and including a transistor gate. Also, the MTP memory cell includes a p-channel capacitor disposed over the p-well and including a capacitor gate. The capacitor gate is coupled to the transistor gate.

P-channel multi-time programmable (MTP) memory cells

Embodiments of a simple and cost-free multi-time programmable (MTP) structure for non-volatile memory cells are presented. The memory cell includes a substrate. A floating gate is disposed over a transistor well. A control gate disposed over a control well is coupled to the floating gate. The control gate includes a control capacitor. A non-self-aligned source/drain (S/D) region is disposed within the transistor well and serves as an erase terminal.

Simple and cost-free MTP structure

Growing community of inventors

Singapore, Singapore

Pengfei Guo