Qualcomm Incorporated

Peng Zou

Syrus Ziai

Gang Ren

Curtis Roger McAllister

Xijian Lin

Joseph Dibene

Anshih Tseng

Curtis Roger Mcallister

An aspect relates to a method of forming an integrated circuit (IC) package, including: forming a thin-film inductor (TFI) over a first dummy carrier wafer; attaching an integrated circuit (IC) die to and over the TFI; attaching a second dummy carrier wafer to and over the IC die; removing the first dummy carrier wafer from the TFI; attaching at least one solder bump to and under the TFI; and removing the second dummy carrier wafer from the IC die. Another aspect relates to a method of forming an IC package, including forming a first redistribution layer (RDL) over a through-silicon via (TSV); forming a second RDL under the TSV; forming a thin-film inductor (TFI) over the first RDL; and attaching at least one integrated circuit (IC) die to the second RDL or the TFI.

Wafer level packaging process for thin film inductors

A semiconductor device has a package substrate, a system-on-chip (SoC) die, and a power management integrated circuit (PMIC) die, arranged in a vertical stack. The SoC die is disposed on a first surface of the package substrate, and the PMIC die is mechanically coupled to a second surface of the package substrate. The PMIC die is electrically coupled to the SOC die via first via connectors of the package substrate and configured to provide DC power to the SOC die via DC connectors electrically coupled to the via connectors of the package substrate. The PMIC die includes thin film inductors, corresponding to the DC connectors, on a surface of the PMIC die and located adjacent to the second surface of the package substrate.

Vertically integrated device stack including system on chip and power management integrated circuit

An electronic device has a power rail that is driven by voltage regulators and provides a rail voltage. Each voltage regulator has an output interface electrically coupled to the power rail to deliver up to a predefined regulator current to the power rail. In each voltage regulator, a voltage regulator controller has an input coupled to the output interface by a feedback path and controls a drive path coupled to the output interface. A bypass unit is coupled to the drive path and voltage regulator controller and operates in a standby mode or an operational mode. In the standby mode, the bypass unit bypasses the feedback path and the respective voltage regulator does not deliver current to the power rail, while in the operational mode, the bypass unit does not bypass the feedback path and the respective voltage regulator delivers up to the predefined regulator current to the power rail.

Management of voltage regulator units in field programmable arrays

A semiconductor device has a power rail that provides a rail voltage. The power rail is electrically coupled to a plurality of voltage regulators, and each voltage regulator includes an output interface electrically coupled to the power rail, and a first drive path and a second drive path both coupled to the output interface, and an intra-regulator balancing circuit. The first and second drive paths are coupled in parallel with each other, and operate during a first phase and a second phase, at an operating frequency, to provide a first path current and a second path current to the power rail, respectively. The intra-regulator balancing circuit senses the first and second path currents and controls a first duty cycle of the first phase and/or a second duty cycle of the second phase based on a difference of the first and second path currents.

Current balancing for voltage regulator units in field programmable arrays

A semiconductor device includes a plurality of voltage regulators arranged in a field programmable array and a power array controller coupled to the plurality of voltage regulators. The power array controller is configured to control the plurality of voltage regulators to output power to a plurality of power rails. Each power rail provides a respective rail current at a respective rail voltage. The power array controller is configured to for each of the plurality of power rails, determine the respective rail current associated with the respective power rail, select a subset of voltage regulators according to at least the respective rail current, and enable the subset of voltage regulators to generate the respective rail voltage and provide the respective rail current collectively.

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Camas, WA, United States of America

Peng Zou