Sandisk Technologies Inc.

Amazon Technologies, Inc.

Ngm Biopharmaceuticals, Inc.

University of Florida Research Foundation, Incorporated

Western Digital Technologies, Inc.

Peng Zhang

Yanli Zhang

Dengtao Zhao

Deepanshu Dutta

Xiang Yang

Raghuveer S Makala

Johann Alsmeier

Swadeshmukul Santra

Jiacen Guo

Darrin Anthony Lindhout

Nan Lu

Jon Paul Dobson

Weihong Tan

Rovelyn Tapec

Thomas Frederick Parsons

Yi Zhang

Huai-Yuan Tseng

Wei Zhao

Ashish Kumar Baraskar

Katrin Kirchhoff

Wei Cao

Zhiping Zhang

Roger Scott Jenke

Arshit Gupta

Dong-il Moon

Yingda Dong

Masaaki Higashitani

James K Kai

Rahul Sharangpani

Liang Li

Ming Hsi Wang

Fei Zhou

Senaka Kanakamedala

Jianchun Dong

Sarath Chandran Puthenthermadam

Hassan Sawaf

Rashmi Gangadharaiah

Muhammad Masuduzzaman

Ramy Nashed Bassely Said

Koichi Matsuno

Xuan Zhong

Yuwen Su

Daniel David Kaplan

Keerti Shukla

Shahram Talakoub

Kalpesh N Sutaria

Meghana Puvvadi

Heguang Li

Jason Krone

Zhaodan Cao

Yarong Lu

Julian E S Salazar

Garima Lalwani

Kartik Natarajan

Shang-Wen Daniel Li

Mona Diab

Adel A Youssef

Niranjhana Nayar

Yi-An Lai

Jon Dobson

To improve programming performance in NAND memory, while maintaining programming accuracy and reducing program disturb, the channel pre-charge phase before a programming pulse can be eliminated. Instead, a read recovery phase after the program verify directly discharges a selected word line from the verify voltage to a negative word line voltage, with non-selected word lines being directly discharged from the read bypass voltage to the negative word line voltage. From the negative word line voltage, the word lines are then ramped up to ground and then on the bias levels of the following programming pulse. These conditions can drive electrons from the charge storage region of the selected memory cell, resulting in a high degree of channel boosting and much less program disturb. Variations of the technique can be applied to NAND memory operable in a sub-block mode where it can be difficult to use the typical channel pre-charge.

Negative word line enabled pre-boosting strategy to improve NAND program performance

An apparatus includes memory cells connected to word lines and disposed in strings each defining a channel and coupled to bit lines and a source line. The memory cells are configured to retain a threshold voltage corresponding to data states. A control means is configured to apply programming pulses followed by verification pulses of program verify voltages associated with the data states to the word lines during a program operation. The control means ramps a selected word line voltage applied to the word lines from one of the program verify voltages to approximately zero while ramping voltages applied to the bit lines and the source line to a high supply voltage during a pre-charge operation. The control means ramps an assist voltage applied to a pre-charge assist portion of the memory apparatus to generate gate-induced drain leakage current in the strings and pre-charge the channel during the pre-charge operation.

Gate-induced drain leakage pre-charge in sub-block mode for three or more tier non-volatile memory structure

A block of non-volatile memory cells is divided into a first sub-block and a second sub-block. Programming non-volatile memory cells of the second sub-block after programming non-volatile memory cells of the first sub-block comprises boosting unselected channels in the second sub-block to a boosted condition; prior to boosting unselected channels in the second sub-block to the boosted condition, boosting unselected channels in the first sub-block to the boosted condition to pre-charge the channels of the second sub-block; and applying a program voltage to a selected word line of the second sub-block while channels in the first sub-block are in the boosted condition and channels in the first sub-block are in the boosted condition.

Non-volatile memory with efficient precharge in sub-block mode

Memory cells of a second sub-block are programmed by pre-charging channels of unselected memory cells connected to the selected word line, boosting the pre-charged channels of unselected memory cells and applying a program voltage to selected non-volatile memory cells connected to the selected word line. The pre-charging includes applying one or more overdrive voltages to word lines connected to memory cells of a first sub-block to provide a conductive path from memory cells of the second sub-block through the first sub-block to a source line and maintaining the word lines connected to memory cells of the first sub-block at one or more overdrive voltages while ramping down signals at the end of the pre-charging. Dummy word lines, positioned between sub-blocks, are maintained at a resting voltage during the boosting in order to cut-off channels of memory cells in the second sub-block from channels of memory cells in the first sub-block.

Non-volatile memory with dummy word line assisted pre-charge

The memory device includes a memory block with a plurality of memory cells that are arranged in a plurality of word lines. The plurality of word lines include a selected word line, a pair of neighboring word lines that are immediately adjacent the selected word line, and a plurality of non-neighboring word lines that are not immediately adjacent the selected word line. Circuitry can perform a sensing operation on at least one memory cell in the selected word line. During the sensing operation, the circuitry is configured to apply a reference voltage to the selected word line, apply different first and second pass voltages to the neighboring word lines, and apply a third pass voltage that is different than the first and second pass voltages to the plurality of non-neighboring word lines. The circuitry is further configured to sense a threshold voltage of the at least one memory cell.

Asymmetric VREADK to reduce neighboring word line interference in a memory device

A storage device is disclosed herein. The storage device comprises: a non-volatile memory, where the non-volatile memory includes a block of N wordlines partitioned into a plurality of sub-blocks and the plurality of sub-blocks includes a first sub-block of a first subset of the block of N wordlines and a second sub-block of a second subset of the block of N wordlines; and control circuitry coupled to the block of N wordlines. The control circuitry is configured to: perform a program operation in a normal order programming sequence on the first sub-block; perform a sensing operation on the first sub-block using a reverse sensing scheme; perform a program operation in a reverse order programming sequence on the second sub-block; and perform a sensing operation on the second sub-block using a regular sensing scheme.

Dual-way sensing scheme for better neighboring word-line interference

The memory device includes a memory block with memory cells arranged in word lines that are divided into sub-blocks. Control circuitry is configured to program each of the word lines of a selected sub-blocks in a plurality of program loops. During at least one program loop, the control circuitry applies a programming pulse to a selected word line. The control circuitry is also configured to simultaneously apply a verify voltage to the selected word line and a pass voltage to unselected word lines. In a first phase of a multi-phase pre-charge process, the control circuitry reduces the voltages applied to the selected word line and at least one unprogrammed word line to a low voltage. In a second phase that follows the first phase, the control circuitry reduces the voltages applied to all word lines that remained at the pass voltage to the low voltage.

Channel pre-charge process in a memory device

Techniques for updating a machine learning model based on user interactions are described. In particular, in some examples, user interactions with a chatbot provide aspects of a data set to be used to train or fine-tune a ML model. In some examples, this is accomplished by collecting data from a first plurality of interactions with a machine learning (ML) model; generating a variant of the ML model using the collected data by: filtering the collected data to create a first data set, training the ML model based on the first data set to generate an adapted ML model, and fine-tuning the adapted ML model on a second data set, different than the first data set to generate the variant of the ML model.

Adaptations of task-oriented agents using user interactions

A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening fill structure including a vertical semiconductor channel and a memory film. The memory film includes a tunneling dielectric layer in contact with the vertical semiconductor channel, a first vertical stack of first dielectric oxide material portions located at levels of the insulating layers and including a dielectric oxide material of a first element, and a second vertical stack of second dielectric oxide material portions located at levels of the electrically conductive layers and including a mixed dielectric oxide material that is a dielectric oxide material of the first element and a second element.

Memory device including mixed oxide charge trapping materials and methods for forming the same

A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a semiconductor material layer, an inter-tier dielectric layer, and a second alternating stack of second insulating layers and second electrically conductive layers located over the inter-tier dielectric layer. A memory opening vertically extends through the second alternating stack, the inter-tier dielectric layer, and the first alternating stack. A memory opening fill structure is located in the memory opening, and includes a first vertical semiconductor channel, a second vertical semiconductor channel, and an inter-tier doped region located between the first and the second semiconductor channel, and providing a first p-n junction with the first vertical semiconductor channel and providing a second p-n junction with the second vertical semiconductor channel.

Three dimensional memory device containing dummy word lines and p-n junction at joint region and method of making the same

In a non-volatile memory system that performs programming of selected memory cells (in coordination with pre-charging and boosting of channels for unselected memory cells) and program-verify to determine whether the programming was successful, the system transitions from program-verify to the next dose of programming by concurrently lowering a voltage applied to a selected word line and voltages applied to word lines on a first side of the selected word line at the conclusion of program-verify. Subsequent to lowering the voltage applied to the selected word line, the system successively lowers voltages applied to groups of one or more word lines on a second side of the selected word line at the conclusion of program-verify beginning with a group of one or more word lines immediately adjacent the selected word line and progressing to other groups of one or more word lines disposed increasingly remote from the selected word line.

Non-volatile memory with one sided phased ramp down after program-verify

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory opening fill structures located within an array of memory openings vertically extending through the alternating stack, and a drain-select-level isolation structure vertically extending through drain-select-level electrically conductive layers between two rows of memory opening fill structures. The drain-select-level isolation structure may comprise a low-k dielectric material or an air gap.

Three-dimensional memory device including low-k drain-select-level isolation structures and methods of forming the same

Techniques are described for a contextual natural language understanding (cNLU) framework that is able to incorporate contextual signals of variable history length to perform joint intent classification (IC) and slot labeling (SL) tasks. A user utterance provided by a user within a multi-turn chat dialog between the user and a conversational agent is received. The user utterance and contextual information associated with one or more previous turns of the multi-turn chat dialog is provided to a machine learning (ML) model. An intent classification and one or more slot labels for the user utterance are then obtained from the ML model. The cNLU framework described herein thus uses, in addition to a current utterance itself, various contextual signals as input to a model to generate IC and SL predictions for each utterance of a multi-turn chat dialog.

Contextual natural language understanding for conversational agents

A spoken language understanding (SLU) system may include an automatic speech recognizer (ASR), an audio feature extractor, an optional synchronizer and a language understanding module. The ASR may produce a first set of input data representing transcripts of utterances. The audio feature extractor may produce a second set of input data representing audio features of the utterances, in particular, non-transcript specific characteristics of the speaker in one or more portions the utterances. The two sets of input data may be provided for the language understanding module to predict intents and slot labels for the utterances. The SLU system may use the optional synchronizer to align the two sets of input data before providing them to the language understanding module.

Multi-modal spoken language understanding systems

A method reading memory using bi-directional sensing, including programming first memory cells coupled to a first word-line using a normal programming order; programming second memory cells coupled to a second word-line using a normal programming order; reading data from the first memory cells by applying a normal sensing operation to the first word-line; and reading data from the second memory cells by applying a reverse sensing operation to the second word-line. Methods also include receiving an error associated with reading data from the first memory cells; and then reading the data from the first memory cells by applying a reverse sensing operation to the first word-line. Method also include receiving an error associated with reading the data from the second memory cells; and then reading the data from the second memory cells by applying a normal sensing operation to the second word-line.

Bi-directional sensing in a memory

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Fremont, CA, United States of America

Peng Zhang