Sandisk Technologies Inc.

Amazon Technologies, Inc.

Ngm Biopharmaceuticals, Inc.

University of Florida Research Foundation, Incorporated

Western Digital Technologies, Inc.

Peng Zhang

Yanli Zhang

Deepanshu Dutta

Dengtao Zhao

Raghuveer S Makala

Johann Alsmeier

Xiang Yang

Swadeshmukul Santra

Darrin Anthony Lindhout

Nan Lu

Jon Paul Dobson

Weihong Tan

Rovelyn Tapec

Thomas Frederick Parsons

Yi Zhang

Huai-Yuan Tseng

Wei Zhao

Ashish Kumar Baraskar

Jiacen Guo

Katrin Kirchhoff

Zhiping Zhang

Roger Scott Jenke

Arshit Gupta

Dong-il Moon

Yingda Dong

Masaaki Higashitani

James K Kai

Rahul Sharangpani

Liang Li

Ming Hsi Wang

Fei Zhou

Senaka Kanakamedala

Jianchun Dong

Sarath Chandran Puthenthermadam

Hassan Sawaf

Muhammad Masuduzzaman

Ramy Nashed Bassely Said

Rashmi Gangadharaiah

Xuan Zhong

Koichi Matsuno

Yuwen Su

Daniel David Kaplan

Keerti Shukla

Shahram Talakoub

Kalpesh N Sutaria

Meghana Puvvadi

Jason Krone

Zhaodan Cao

Yarong Lu

Julian E S Salazar

Garima Lalwani

Kartik Natarajan

Shang-Wen Daniel Li

Mona Diab

Adel A Youssef

Niranjhana Nayar

Yi-An Lai

Jon Dobson

The memory device includes a memory block with memory cells arranged in word lines that are divided into sub-blocks. Control circuitry is configured to program each of the word lines of a selected sub-blocks in a plurality of program loops. During at least one program loop, the control circuitry applies a programming pulse to a selected word line. The control circuitry is also configured to simultaneously apply a verify voltage to the selected word line and a pass voltage to unselected word lines. In a first phase of a multi-phase pre-charge process, the control circuitry reduces the voltages applied to the selected word line and at least one unprogrammed word line to a low voltage. In a second phase that follows the first phase, the control circuitry reduces the voltages applied to all word lines that remained at the pass voltage to the low voltage.

Channel pre-charge process in a memory device

Techniques for updating a machine learning model based on user interactions are described. In particular, in some examples, user interactions with a chatbot provide aspects of a data set to be used to train or fine-tune a ML model. In some examples, this is accomplished by collecting data from a first plurality of interactions with a machine learning (ML) model; generating a variant of the ML model using the collected data by: filtering the collected data to create a first data set, training the ML model based on the first data set to generate an adapted ML model, and fine-tuning the adapted ML model on a second data set, different than the first data set to generate the variant of the ML model.

Adaptations of task-oriented agents using user interactions

A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening fill structure including a vertical semiconductor channel and a memory film. The memory film includes a tunneling dielectric layer in contact with the vertical semiconductor channel, a first vertical stack of first dielectric oxide material portions located at levels of the insulating layers and including a dielectric oxide material of a first element, and a second vertical stack of second dielectric oxide material portions located at levels of the electrically conductive layers and including a mixed dielectric oxide material that is a dielectric oxide material of the first element and a second element.

Memory device including mixed oxide charge trapping materials and methods for forming the same

A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a semiconductor material layer, an inter-tier dielectric layer, and a second alternating stack of second insulating layers and second electrically conductive layers located over the inter-tier dielectric layer. A memory opening vertically extends through the second alternating stack, the inter-tier dielectric layer, and the first alternating stack. A memory opening fill structure is located in the memory opening, and includes a first vertical semiconductor channel, a second vertical semiconductor channel, and an inter-tier doped region located between the first and the second semiconductor channel, and providing a first p-n junction with the first vertical semiconductor channel and providing a second p-n junction with the second vertical semiconductor channel.

Three dimensional memory device containing dummy word lines and p-n junction at joint region and method of making the same

In a non-volatile memory system that performs programming of selected memory cells (in coordination with pre-charging and boosting of channels for unselected memory cells) and program-verify to determine whether the programming was successful, the system transitions from program-verify to the next dose of programming by concurrently lowering a voltage applied to a selected word line and voltages applied to word lines on a first side of the selected word line at the conclusion of program-verify. Subsequent to lowering the voltage applied to the selected word line, the system successively lowers voltages applied to groups of one or more word lines on a second side of the selected word line at the conclusion of program-verify beginning with a group of one or more word lines immediately adjacent the selected word line and progressing to other groups of one or more word lines disposed increasingly remote from the selected word line.

Non-volatile memory with one sided phased ramp down after program-verify

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory opening fill structures located within an array of memory openings vertically extending through the alternating stack, and a drain-select-level isolation structure vertically extending through drain-select-level electrically conductive layers between two rows of memory opening fill structures. The drain-select-level isolation structure may comprise a low-k dielectric material or an air gap.

Three-dimensional memory device including low-k drain-select-level isolation structures and methods of forming the same

Techniques are described for a contextual natural language understanding (cNLU) framework that is able to incorporate contextual signals of variable history length to perform joint intent classification (IC) and slot labeling (SL) tasks. A user utterance provided by a user within a multi-turn chat dialog between the user and a conversational agent is received. The user utterance and contextual information associated with one or more previous turns of the multi-turn chat dialog is provided to a machine learning (ML) model. An intent classification and one or more slot labels for the user utterance are then obtained from the ML model. The cNLU framework described herein thus uses, in addition to a current utterance itself, various contextual signals as input to a model to generate IC and SL predictions for each utterance of a multi-turn chat dialog.

Contextual natural language understanding for conversational agents

A spoken language understanding (SLU) system may include an automatic speech recognizer (ASR), an audio feature extractor, an optional synchronizer and a language understanding module. The ASR may produce a first set of input data representing transcripts of utterances. The audio feature extractor may produce a second set of input data representing audio features of the utterances, in particular, non-transcript specific characteristics of the speaker in one or more portions the utterances. The two sets of input data may be provided for the language understanding module to predict intents and slot labels for the utterances. The SLU system may use the optional synchronizer to align the two sets of input data before providing them to the language understanding module.

Multi-modal spoken language understanding systems

A method reading memory using bi-directional sensing, including programming first memory cells coupled to a first word-line using a normal programming order; programming second memory cells coupled to a second word-line using a normal programming order; reading data from the first memory cells by applying a normal sensing operation to the first word-line; and reading data from the second memory cells by applying a reverse sensing operation to the second word-line. Methods also include receiving an error associated with reading data from the first memory cells; and then reading the data from the first memory cells by applying a reverse sensing operation to the first word-line. Method also include receiving an error associated with reading the data from the second memory cells; and then reading the data from the second memory cells by applying a normal sensing operation to the second word-line.

Bi-directional sensing in a memory

Apparatuses and techniques are described for increasing channel boosting of NAND string during programming by applying a periodic low word line bias during programming. In one aspect, a low pass voltage, VpassL, is applied to designated word lines to create periodic low points or dips in the channel boosting level. A normal pass voltage, Vpass, is applied to other unselected word lines. The low points create barriers to the movement of electrons in the channel toward the selected word line, to prevent the electrons from pulling down the voltage at the channel region which is adjacent to the selected word line. VpassL can be applied to designated word lines at the source and/or drain sides of the selected word line. A control circuit can be configured with various parameters for implementing the techniques.

Periodic reduced word line bias which increases channel boosting

A memory device disclosed herein. The memory device comprises: a memory string including a first select transistor, a memory cell transistor, and a second select transistor connected in series; a bit line connected to one end of the first select transistor; a source line connected to one end of the second select transistor; a first select line connected to a gate of the first select transistor; a word line connected to a gate of the memory cell transistor; a second select line connected to a gate of the second select transistor; and a control circuit configured to perform, before a program operation, a pre-charge operation comprising: applying a voltage to the second select line connected to the gate of the second select transistor to cause gate-induced drain leakage from the second select transistor.

Hole pre-charge scheme using gate induced drain leakage generation

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, where the electrically conductive layers comprise word lines located between a source select gate electrode and a drain select gate electrode, a memory opening vertically extending through each layer of the alternating stack to a top surface of the substrate, a memory film and vertical semiconductor channel having a doping of a first conductivity type located in the memory opening, and an active region having a doping of a second conductivity type that is an opposite of the first conductivity type and adjoined to an end portion of the vertical semiconductor channel to provide a p-n junction. The end portion of the vertical semiconductor channel has a first thickness, and a middle portion of the vertical semiconductor channel has a second thickness which is less than the first thickness.

Three-dimensional memory device containing structures for enhancing gate-induced drain leakage current and methods of forming the same

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, and memory stack structures extending through the alternating stack. Each of the memory stack structures contains a memory film and a vertical semiconductor channel. At least one of the electrically conductive layers contains a first conductive material portion having a respective inner sidewall that contacts a respective one of the memory films at a vertical interface, and a second conductive material portion that has a different composition from the first conductive material portion, and contacting the first electrically conductive material portion. The first conductive material portion has a lower work function than the second conductive material portion.

Three-dimensional memory device containing plural work function word lines and methods of forming the same

A head-mounted wearable device (HMWD) provides audio output from a first speaker that is driven with a first signal and a second speaker that is driven with a second signal. Based on a volume level setting, an equalization profile and inversion frequency are determined. The equalization profile selectively amplifies or attenuates particular frequencies or ranges of frequencies. Those frequencies in the second signal that are above the inversion frequency have their amplitude inverted, relative to the first signal. When driven by the first signal and the second signal, the first speaker and the second speaker operate as acoustic dipoles below the inversion frequency and acoustic quadrupoles above the inversion frequency. Sound from the first and second speakers with frequencies above the inversion frequency exhibits destructive interference. As a result, the user wearing the HMWD is able hear audio output while audio amplitude perceived by the bystanders is significantly reduced.

System for presentation of audio using wearable device

Growing community of inventors

Fremont, CA, United States of America

Peng Zhang