Inventec Corp.

Inventec (Pudong) Technology Corporation

Peng Zhan

Fang-Jie Chu

Ji-Peng Xu

Xiaogang Lu

Li-Hong Huang

Ying Qian

Jiang-Tao Yuan

A complex programmable logic device includes a SGPIO analyzing circuit, a IC analyzing circuit and a first multiplexer. The SGPIO analyzing circuit has a plurality of port analyzing circuits, a detecting circuit and a processing circuit. Each port analyzing circuit receives an input signal and outputs a first data. The detecting circuit detects the input signal of the first port analyzing circuit to output a detecting signal. The processing circuit captures port information of the first data outputted by at least part of the port analyzing circuits as a first control signal according to the detecting signal. The IC analyzing circuit analyzes a data flow for outputting a second control signal according to an address command related to an address message, a control command and an input data. The first multiplexer selects the first control signal or the second control to be outputted according to a testing signal.

Complex programmable logic device and operation method thereof

A power control device comprises the following elements. An input assembly has a switch and is electrically connected to a first actuator, and generates a trigger signal according to a state of the switch or a control signal inputted from the first actuator. A calculating assembly is electrically connected to the input assembly and outputs a first signal from a control output terminal and a second signal from a feedback output terminal when the calculating assembly receives the trigger signal. An output assembly is electrically connected to the control output terminal of the calculating assembly for receiving the first signal and changes a power-on/off state of a controlled device when a voltage level of the first signal changes. A feedback assembly is electrically connected to the feedback output terminal of the calculating assembly and outputs a feedback signal to the first actuator according to the second signal.

Power control device and a control method

A fan control circuit comprises: a fan controller connected with at least one fan connector, connected with a baseboard management controller (BMC) via integrated circuit bus communication lines and outputting a BMC fan signal wherein said fan controller is powered by a main power supply, and a baseboard status detection circuit connected with the BMC and the fan controller respectively, detecting a heartbeat signal of the BMC, and controlling an output of a fan pulse signal according to the heartbeat signal so as to control a fan connected with the fan controller to operate normally.

Fan control circuit and fan control system

The invention provides server including a casing. The casing has back panel area. The back panel area is located at air outlet of the server. Package substrate, up HDD back panel and down HDD back panel are horizontally disposed on the back panel area. Motherboard of the server is communicatively connected to the package substrate via first connector. The package substrate is communicatively connected to the up HDD back panel via second connector. The up HDD back panel is communicatively connected to the down HDD back panel via third connector. The server of the invention has high dense storage devices, very high space utilization, and innovative heat dissipation channels design. The server has high configuration flexibility and expansibility, can be operated in a simple manner, and can support apparatus that are power-consuming and operating in standby mode.

Server

A complex programmable logic device with capability of performing multi-address response includes a IC slave circuit, a first multiplexer, a plurality of second multiplexers and a plurality of register circuits. The IC slave circuit outputs an address message and an input data by analyzing a data flow. The address message is responsive to one of a plurality of predetermined addresses, and the IC slave circuit outputs the predetermined address to which the address message is responsive as an address command as well as the input data. The first multiplexer outputs the input data to a respective one of the plurality of second multiplexers according to the address command. The second multiplexer received the input data accesses to a register unit included in a respective one of the register circuits according to the input data.

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Shanghai, China

Peng Zhan