International Business Machines Corporation

Google Inc.

Monolithic Power Systems, Inc.

Adeia Semiconductor Bonding Technologies Inc.

Elpis Technologies Inc.

Amazon Technologies, Inc.

Globalfoundries Inc.

Honda Motor Co., Ltd.

Adeia Semiconductor Solutions LLC

Tessera LLC

Peng Xu

Kangguo Cheng

Juntao Li

Zhenxing Bi

Choonghyun Lee

Heng Wu

Chen Zhang

Xin Miao

Sivananda K Kanakasabapathy

Chun Wing Yeung

Huiming Bu

Jie Yang

Zuoguang Liu

Chi-Chun Liu

Andrew Mark Greene

Xuefeng Liu

Franz Josef Och

Jeffrey Adgate Dean

Dechao Guo

Wenyu Xu

Fee Li Lie

Thorsten Brants

Nicolas J Loubet

Shogo Mochizuki

Su Chen Fan

Yongan Xu

Huimei Zhou

Ruilong Xie

John Ryan Sporre

Jay Michael Ponte

Alexander Mark Franz

Jeffrey Chin

Sebastian Naczas

Daniel Rosart

Sha-Mayn Teh

John S Hawkins

Karel Driesen

Ignacio E Thayer

Anton Carver

Zheng Xu

Ekmini Anuja De Silva

Yann Mignot

Donald Francis Canaperi

Thamarai Selvi Devarajan

Junli Wang

Wei P Chen

Yi Song

Yan Dong

Jingyun Zhang

Cheng Chi

Sudipta Sengupta

Ciprian Ioan Chelba

Jay William Strane

Gen Tsutsui

Bing Xiang

Hao Tang

Ryan O Jung

Alexander Jay Cuthbert

Jinghai Zhou

Ashok Chhabedia Popat

Ramesh M Nallapati

Fernando Pereira

Zhiguo Wang

Xiaofei Ma

Chanro Park

Ruqiang Bao

Xunyuan Zhang

Yuancheng Ren

Kaiwei Yao

Kikuo Fujimura

James Copland Moyer

James Nguyen

Sergey Levine

Jian Jiang

Awaneesh Verma

Joshua James Estelle

Honggang Sheng

Wolfgang Macherey

Cicero Nogueira Dos Santos

Alireza Nakhaei Sarvedani

Shankar Kumar

Patrick Ng

Jie Tan

Chia-Hsin Chang

Francis Yu

Terry Hook

Saurabh Kumar Singh

Dimitrios Soulios

Yong Yuan

Sehoon Ha

Zhiheng Huang

Krishnakumar Rajagopalan

Ioannis Tsochandaridis

Ankit Sultania

Dong Wang

Richard Zens

Jean-Pierre Dodel

Milan Saini

Zhenyu Tan

Inner and outer spacers for nanosheet transistors are formed using techniques that improve junction uniformity. One nanosheet transistor device includes outer spacers and an interlevel dielectric layer liner made from the same material. A second nanosheet transistor device includes outer spacers, inner spacers and an interlevel dielectric layer liner that are all made from the same material.

Nanosheet transistor

A method of forming stacked vertical field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first spacer layer on the substrate, a first protective liner on the first spacer layer, a first gap layer on the first protective liner, a second protective liner on the first gap layer, a second spacer layer on the second protective liner, a sacrificial layer on the second spacer layer, a third spacer layer on the sacrificial layer, a third protective liner on the third spacer layer, a second gap layer on the third protective liner, a fourth protective liner on the second gap layer, and a fourth spacer layer on the fourth protective liner. The method further includes forming channels through the layer stack, a liner layer on the sidewalls of the channels, and a vertical pillar in the channels.

Three-dimensional field effect device

Techniques are disclosed that enable training a plurality of policy networks, each policy network corresponding to a disparate robotic training task, using a mobile robot in a real world workspace. Various implementations include selecting a training task based on comparing a pose of the mobile robot to at least one parameter of a real world training workspace. For example, the training task can be selected based on the position of a landmark, within the workspace, relative to the pose. For instance, the training task can be selected such that the selected training task moves the mobile robot towards the landmark.

System and methods for training robot policies in the real world

A semiconductor device includes one or more fins. Each fin includes a top channel portion formed from a channel material, a middle portion, and a bottom substrate portion formed from a same material as an underlying substrate. An oxide layer is formed between the bottom substrate portion of each fin and the isolation layer, with a space between a sidewall of at least a top portion of the isolation dielectric layer and an adjacent sidewall of the one or more fins, above the oxide layer. A gate dielectric, protruding into the space and in contact with the middle portion, is formed over the one or more fins and has a portion formed from a material different from the oxide layer.

Forming a sacrificial liner for dual channel devices

A method of forming stacked fin field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first semiconductor layer on a surface of the substrate, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, a separation layer on the third semiconductor layer, a fourth semiconductor layer on the separation layer, a fifth semiconductor layer on the fourth semiconductor layer, and a sixth semiconductor layer on the fifth semiconductor layer. The method further includes forming a plurality of channels through the layer stack to the surface of the substrate, and removing portions of the second semiconductor layer and fifth semiconductor layer to form lateral grooves.

Semiconductor devices and methods of forming a first layer cap at ends of layers of first channel material in a stack of alternating layers of first channel material and second channel material. A second layer cap is formed at ends of the layers of second channel material. The first layer caps are etched away in a first device region. The second layer caps are etched away in a second device region.

Hybrid-channel nano-sheet FETs

Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes performing fabrication operations to form a field effect transistor (FET) device on a substrate. The fabrication operations include forming a channel region over the substrate, forming a bottom conductive layer of a wrap-around source or drain (S/D) contact over the substrate, and forming a S/D region over the bottom conductive layer and adjacent to the channel region. The S/D region is communicatively coupled to the channel region and the bottom conductive layer.

Transistor having wrap-around source/drain contacts

A system and method for providing probabilistic-based lane-change decision making and motion planning that include receiving data associated with a roadway environment of an ego vehicle. The system and method also include performing gap analysis to determine at least one gap between neighboring vehicles that are traveling within the target lane to filter out an optimal merging entrance for the ego vehicle to merge into the target lane and determining a probability value associated with an intention of a driver of a following neighboring vehicle to yield to allow the ego vehicle to merge into the target lane. The system and method further include controlling the ego vehicle to autonomously continue traveling within the current lane or autonomously merge from current lane to the target lane based on at least one of: if the optimal merging entrance is filtered out and if the probability value indicates an intention of the driver to yield.

Probabilistic-based lane-change decision making and motion planning system and method thereof

Techniques for fabricating a volatile memory structure having a transistor and a memory component is described. The volatile memory structure comprises the memory component formed on a substrate, wherein a first shape comprising one or more pointed edges is formed on a first surface of the memory component. The volatile memory structure further comprises transistor formed on the substrate and electrically coupled to the memory component to share operating voltage, wherein operating voltage applied to the transistor flows to the memory component.

Resistive random-access memory

A semiconductor device and method for forming the same. The device comprises at least a dielectric layer, a two-dimensional (2D) material layer, a gate structure, and source/drain contacts. The 2D material layer contacts the dielectric layer. The gate structure contacts the 2D material layer. The source/drain contacts are disposed above the 2D material layer and contact the gate structure. The method includes forming a structure including at least a handle wafer, a 2D material layer, a gate structure in contact with the 2D material layer, an insulating layer, and a sacrificial layer. A portion of the sacrificial layer is etched. An inter-layer dielectric is formed in contact with the insulating layer and sidewalls of the sacrificial layer. The sacrificial layer and a portion of the insulating layer are removed. Source and drain contacts are formed in contact with the portion of the 2D material layer.

Self-aligned two-dimensional material transistors

Semiconductor devices and methods for forming the semiconductor devices include forming a sacrificial layer on a substrate on each side of a stack of nanosheets, the stack of nanosheets including first nanosheets and second nanosheets stacked in alternating fashion with a dummy gate structure formed thereon. Source and drain regions are grown on from the sacrificial layer and from ends of the second nanosheets to form source and drain regions in contact with each side of the stack of nanosheets. The sacrificial layer is removed. An interlevel dielectric is deposited around the source and drain regions to fill between the source and drain regions and the substrate.

Source and drain epitaxy and isolation for gate structures

Techniques for generation of synthetic queries from customer data for training of document querying machine learning (ML) models as a service are described. A service may receive one or more documents from a user, generate a set of question and answer pairs from the one or more documents from the user using a machine learning model trained to predict a question from an answer, and store the set of question and answer pairs generated from the one or more documents from the user. The question and answer pairs may be used to train another machine learning model, for example, a document ranking model, a passage ranking model, a question/answer model, or a frequently asked question (FAQ) model.

Systems, apparatuses, and methods to generate synthetic queries from customer data for training of document querying machine learning models

A method of forming vertical fins on a substrate at the same time, the method including, forming a mask segment on a first region of the substrate while exposing the surface of a second region of the substrate, removing a portion of the substrate in the second region to form a recess, forming a fin layer in the recess, where the fin layer has a different material composition than the substrate, and forming at least one vertical fin on the first region of the substrate and at least one vertical fin on the second region of the substrate, where the vertical fin on the second region of the substrate includes a fin layer pillar formed from the fin layer and a substrate pillar.

Fabrication of fin field effect transistors utilizing different fin channel materials while maintaining consistent fin widths

Techniques for searching documents are described. An exemplary method includes receiving a document search query; querying at least one index based upon the document search query to identify matching data; fetching the identified matched data; determining one or more of a top ranked passage and top ranked documents from the set of documents based upon one or more invocations of one or more machine learning models based at least on the fetched identified matched data and the document search query; and returning one or more of the top ranked passage and the proper subset of documents.

Systems, apparatuses, and methods for document querying

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Guilderland, NY, United States of America

Peng Xu