Sandisk Technologies Inc.

Peng Wang

Jia Li

Bo Lei

Yihang Liu

Jun Wan

Long C Pham

Zhenni Wan

Keyur Payak

Behrang Bagheri

The memory device includes a memory block with a plurality of memory cells that are arranged in a plurality of word lines. The word lines are grouped in a plurality of layers. The memory device also includes circuitry that is configured to program the memory cells of a selected word line of the plurality of word lines. The circuitry is configured during programming to determine which layer of the plurality of layers the selected word line is located in. The circuitry is also configured to apply a programming voltage to the selected word line and apply pass voltages to a plurality of unselected word lines. For at least some of the unselected word lines, the pass voltage is a baseline pass voltage level that is adjusted by a layer-unique bias pass voltage.

VPASS auto layer compensation in a memory device

During a read operation for memory cells connected a selected word line, a memory system adjusts the overdrive voltage applied to word lines adjacent the selected word line in order to compensate for margin degradation between the erased data state and the lowest programmed data state.

Non-volatile memory with overdrive voltage zoning to compensate for reduced margins

An apparatus that comprises a plurality of memory cells and a control circuit coupled to the plurality of memory cells is disclosed. The control circuit is configured to perform a read operation. The read operation includes determining a read condition of a memory cell, where the read condition is of a plurality of read conditions and determining a boost timing for the memory cell, where the boost timing corresponds to the read condition.

Method to optimize first read versus second read margin by switching boost timing

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San Jose, CA, United States of America

Peng Wang