Tensilica, Inc.

Intel Corporation

Peng Tu

Darin Stamenov Petkov

William A Huffman

Christopher Rowen

Earl A Killian

Dror E Maydan

David W Goodwin

Himanshu A Sanghavi

Ding-Kai Chen

Steven Weng-Kiang Tjiang

James Robert Kennedy

Cheng C Wang

Youfeng Wu

Tatiana Shpeisman

Victor W Lee

Paul M Petersen

Arch D Robison

Hongbo Rong

Todd A Anderson

Hai Liu

P G Lowney

Technologies for generating composable library functions include a first computing device that includes a library compiler configured to compile a composable library and second computing device that includes an application compiler configured to compose library functions of the composable library based on a plurality of abstractions written at different levels of abstractions. For example, the abstractions may include an algorithm abstraction at a high level, a blocked-algorithm abstraction at medium level, and a region-based code abstraction at a low level. Other embodiments are described and claimed herein.

Technologies for low-level composable high performance computing libraries

A digital computer system automatically creates an Instruction Set Architecture (ISA) that potentially exploits VLIW instructions, vector operations, fused operations, and specialized operations with the goal of increasing the performance of a set of applications while keeping hardware cost below a designer specified limit, or with the goal of minimizing hardware cost given a required level of performance.

Automatic instruction set architecture generation

A processor can achieve high code density while allowing higher performance than existing architectures, particularly for Digital Signal Processing (DSP) applications. In accordance with one aspect, the processor supports three possible instruction sizes while maintaining the simplicity of programming and allowing efficient physical implementation. Most of the application code can be encoded using two sets of narrow size instructions to achieve high code density. Adding a third (and larger, i.e. VLIW) instruction size allows the architecture to encode multiple operations per instruction for the performance critical section of the code. Further, each operation of the VLIW format instruction can optionally be a SIMD operation that operates upon vector data. A scheme for the optimal utilization (highest achievable performance for the given amount of hardware) of multiply-accumulate (MAC) hardware is also provided.

Vector co-processor for configurable and extensible processor architecture

Load/store operation of memory misaligned vector data using alignment register storing realigned data portion for combining with remaining portion

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San Ramon, CA, United States of America

Peng Tu