Kaneka Corporation

The Texas A&m University System

Carnegie Mellon University

Gradient Design Automation Inc.

Peng Li

Rajit Chandra

Xin Liang Li

Hung-Jue Sue

Larry Pileggi

Mehdi Asheghi

Yang Xu

Lawrence Thomas Pileggi

Masahiro Miyamoto

Riichi Nishimura

Shinsuke Akao

Lawrence Piileggi

Minhao Wong

A coating composition and coating products made therefrom, containing modified inorganic nanoplatelets that form mesomorphic structure in a resin phase. The coating products exhibit low permeation/penetration properties, and can be used as anti-corrosion or barrier coatings.

Coating compositions and coating products made therefrom

A method of manufacturing a nanocomposite having a continuous organic phase and oligomer-modified nanoplatelet mesomorphic structures, wherein the oligomer has a molecular weight of at least 100 g/mol.

Surface-modified, exfoliated nanoplatelets as mesomorphic structures in solutions and polymeric matrices

A method and apparatus for modeling and thermal analysis of semiconductor chip designs is provided. One embodiment of a novel method for performing thermal testing of a semiconductor chip design includes calculating full-chip temperatures over the semiconductor chip design (e.g., to identify steep thermal gradients) and modeling the full-chip temperatures in accordance with a geometric multi-grid technique. The geometric multi-grid technique is tailored to determine temperatures within the semiconductor chip design based at least in part on the physical attributes or geometry of the design.

Method and apparatus for thermal modeling and analysis of semiconductor chip designs

The present invention is a method and apparatus for creating a reduced-order IC interconnect model, which incorporates variations in interconnect process parameters, and models both on-chip and off-chip interconnects. The method is based on mathematically representing an IC interconnect system, including mathematical interconnect process parameter terms, which are manipulated to facilitate simplification of an IC interconnect model. The IC interconnect model is then simplified by using a mathematical technique called state-space projection. Specifically, an IC interconnect system is represented with at least one modified nodal analysis equation (MNA) that is based on frequency, interconnect process parameters are added and substituted back into the MNA(s), terms with interconnect process parameters are explicitly matched. A state-space projection is created, which implicitly matches frequency terms. The state-space projection is used to create the reduced-order IC interconnect model.

Method for parameterized model order reduction of integrated circuit interconnects

Analog and radio frequency system-level simulation using frequency relaxation. Embodiments of the invention use a frequency relaxation approach for analog/RF system-level simulation that accommodates both large system size and complex signal space. The simulator can determine an output response for a system by partitioning the system into blocks and simulating the propagation of an input signal through the blocks. The input signal can take various forms, including a multi-tone sinusoidal signal, a continuous spectra signal, and/or a stochastic signal. Frequency relaxation is applied to produce individual responses. The output response can be computed based on obtaining convergence of the individual responses. The input to embodiments of the simulator can be a circuit netlist, or a block-level macromodel.

Analog and radio frequency (RF) system-level simulation using frequency relaxation

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College Station, TX, United States of America

Peng Li