Realtek Semiconductor Inc.

Moai Electronics Corporation

Midas Mana Technology Sdn.bhd.

Peng-Fei Lin

Tsung-Han Tsai

Ming-Chi Lin

Shih-Chang Chen

Ming-Hung Wang

Kuo-Wei Chi

Chen-Yuan Chang

Po-Hao Yu

Kuo-Chen Chuang

A phase interpolation device and a multi-phase clock generation device are provided. The phase interpolation device includes a digital controller circuit and a phase interpolator that includes a capacitor and circuit branches, which are controlled by the digital controller circuit to generate an n-th phase clock of N phase clocks between first and second input clocks. When the n-th phase clock is generated, the digital controller circuit controls, in response to appearances of rising edges of the first input clock, the circuit branches to charge the capacitor using (N−n+1)×M ones of the first current source, and controls, in response to appearances of rising edges of the second input clock, the circuit branches to use N×M ones of the first current source to charge the capacitor. N, M, n are integers.

Phase interpolation device and multi-phase clock generation device

A slew rate control device and a slew rate control method are provided. The slew rate control device includes a signal generating circuit, a comparator circuit, and a control circuit. The signal generating circuit generates a first voltage signal and a second voltage signal having a slew rate, and the first voltage signal and the second voltage signal are a pair of differential signals. The comparator circuit outputs an enabling signal according to a relative positional relationship between an eye crossing point of the pair of differential signals and a signal edge of a reference clock. The control circuit generates at least one control signal according to the enabling signal to control the signal generating circuit, such that the signal generating circuit changes the slew rate of the first voltage signal and the second voltage signal according to the at least one control signal.

Slew rate control device and slew rate control method

The present invention discloses a receive data equalization apparatus. A delay-compensating calculation circuit retrieves training data groups of a training data signal to retrieve total delay amount, generate signed compensation amounts according to a relation among training data contents of training data in each of the training data groups to generate total compensation amount accordingly, and solve equations that correspond total delay amount of the training data groups to the total compensation amount to obtain each of the compensation amounts. A receive data equalization circuit receives the compensation amounts and retrieves a receive data group in a receive data signal, generate signed receive compensation amounts according to a relation among receive data contents of receive data in the receive data group to generate a total receive compensation amount accordingly to perform equalization on a terminal edge of the receive data group according to the total receive compensation amount.

Received data equalization apparatus and method

A phase-locked loop (PLL) with novel phase detection mechanism is provided, including a phase frequency detector (PFD), a controller, a digital-to-analog (D2A) module, and a voltage-controlled oscillator/current-controlled oscillator (VCO/ICO), wherein PFD has a reference signal input and an input from the output signal of the VCO/ICO and is connected to the controller, the controller is then further connected to the D2A module, the D2A module converts the control signal from the controller into an analog voltage to control the frequency and phase of VCO/ICO. It is worth noting that the PFD of the present invention has a novel phase detection mechanism so that the phase detection can be accomplished by observing signal level transitions of the reference signal input and a delayed reference signal with respect to the output signal of the VCO/ICO without edge alignment. In addition, the novel phase detection mechanism also allows flexible reference signal input.

Phase-locked loop with novel phase detection mechanism

USB device

An apparatus for generating multi-phase clock signals with a ring oscillator is provided, including a first stage phase-blender module and a second stage phase-blender module. The first stage phase-blender module further includes a plurality of differential OP phase-blender circuits. Each differential blender circuit has two signal inputs, and an output signal whose phase is an interpolation of the two input signals. The second stage phase blender module includes a plurality of inverter phase-blender circuits. Each inverter phase-blender circuit receives two output signals from the first stage phase-blender module as inputs, and outputs a clock signal with the interpolated phase of the two output signals of the first stage phase-blender module.

Ring oscillator with a two-stage phase blender for generating multi-phase clock signals

An apparatus and method for automatically switching between USB host and device is provided. In a device with a USB interface, the present invention automatically switches between a USB host and USB device by detecting the handshake protocol of the D+ and D&#x2212; pins of the USB interface. The apparatus for automatically switching between USB host and device includes ah host mode element, a device mode element, a random auto-switcher, and a detection element. The random auto-switcher switches the connection to the host mode element or the device mode element at random time. The detection element monitors the handshake protocol of the D+ and D&#x2212; pins of USB interface and the external USB-interface device to determine whether the host mode or the device mode is in use. When the present invention detects the external USB-interfaced device is a host, the present invention switches to become a USB device. Similarly, when the present invention detects the external USB-interfaced device is a USB device, the present invention switches to become a USB host.

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Hsinchu, Taiwan

Peng-Fei Lin