Advanced Micro Devices Corporation

Peng Fang

John T Yue

Hao Fang

Jiang Tao

Matthew S Buynoski

Ming-Ren Lin

Yowjuang William Liu

Donald L Wollesen

Emi Ishida

Sunil Narayan Shabde

Homi Fatemi

A test system and methodology to improve the performance and reliability of critical paths including stacked NAND gates with sub-minimum channel transistors employs one or more inverter based ring oscillators to generate reliability data. The reliability data is used to calibrate an aged transistor model, which describes the hot carrier reliability of sub-minimum channel length transistors. A computer simulation uses the calibrated, aged transistor model to simulate the critical path circuitry including the stacked NAND gates.

Test system and methodology to improve stacked NAND gate based critical path performance and reliability

A field effect transistor is formed across a one or more trenches (,) or bars (,), thereby increasing the effective width of the channel region and the current-carrying capacity of the device.

Bar field effect transistor

A semiconductor device having reduced hot carrier degradation is achieved by doping the semiconductor substrate and gate oxide with deuterium. A conventional semiconductor device is formed with sequentially deposited metal layers and dielectric layers and a topside protective dielectric layer deposited thereon. Deuterium is introduced to the semiconductor device by using deuterium-containing reactants in at least one of the semiconductor manufacturing steps to passivate dangling silicon bonds at the silicon/oxide interface region.

Deuterium doping for hot carrier reliability improvement

Asymmetrically doped source/drain regions of a transistor are formed employing protective insulating layers to prevent a portion of the gate electrode from receiving an excessive impurity implantation dose and penetrating through the underlying gate insulating layer into the semiconductor substrate. Sidewall spacers are employed during heavy implantation.

Method of forming asymmetrically doped source/drain regions

A method for determining a reliable gate oxide thickness for a transistor involves subjecting test transistors to an alternating current (AC) voltage until the test transistors break down. The breakdown times of the test transistors are measured and correlated with the corresponding gate oxide thickness of the test transistor to form a reliability model of the transistor. The reliable gate oxide thickness is determined by extrapolating the reliability model out to a predetermined period of time for which reliability is desired, for example, ten years.

Method for determining a reliable oxide thickness

Plasma induced degradation of thin gate dielectric layers, e.g., silicon dioxide layers of less than 50 .ANG., is assessed by impressing a constant current density across the gate dielectric layer and measuring the resulting stress induced leakage current as a function of time. The sensitivity of the stress induced leakage current to traps generated in a thin gate dielectric layer enables the use of stress induced leakage current measurements to monitor plasma induced damage during various phases of semiconductor manufacturing.

Assessing plasma induced gate dielectric degradation with stress induced

There is provided an improved metallization stack structure so as to produce a higher electromigration resistance and yet maintain a relatively low resistivity. The metallization stack structure includes a pure copper layer sandwiched between a top thin doped copper layer and a bottom thin doped copper layer. The top and bottom thin doped copper layers produce a higher electromigration resistance. The pure copper layer produces a relatively low resistivity.

Metallization stack structure to improve electromigration resistance and

A method of forming low dielectric insulation between pairs of conductive lines separated by insulating material of a level of interconnection for integrated circuits by selectively removing portions of the insulating material to create spaces for containing a gas with a dielectric constant of slightly above 1. Preferably, the insulating material is a conformal source of silicon oxide, such as tetraethylorthosilicate. The resultant method forms an insulation separating the conductive lines whose composite dielectric constant with the gas in the spaces between the insulating material is not greater than about 3 over a predetermined distance. An integrated circuit having a plurality of semiconductor devices being interconnected by conductive lines separated by insulating material and spaces containing a gas, composite dielectric constant of which is not greater than about 3 over a predetermined distance.

Interlevel dielectric with multiple air gaps between conductive lines of

A field effect transistor is formed across one or more trenches (26) or bars (120), thereby increasing the effective width of the channel region and the current-carrying capacity of the device.

There is provided an improved metallization stack structure and a method for fabricating the same so as to produce a higher electromigration resistance and yet maintain a relatively low resistivity. The metallization stack structure includes a pure copper layer sandwiched between a top thin doped copper layer and a bottom thin doped copper layer. The top and bottom thin doped copper layers produce a higher electromigration resistance. The pure copper layer produces a relatively low resistivity.

Method for fabricating a metallization stack structure to improve

A test method and apparatus are provided for predicting hot-carrier induced leakage over time in IGFET's. Test results are used to show how choice of channel length and stress voltages critically affect hot-carrier-induced leakage (HCIL) leakage over time, particularly in devices having submicron channel lengths. Models are developed for predicting leakage current over the long term given short term test results. Alternative design strategies are proposed for reliably satisfying long term leakage requirements.

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San Jose, CA, United States of America

Peng Fang