Southeast University

Jiangsu Province Institute of Traditional Chinese Medicine

Peng Cao

Longxing Shi

Jun Yang

Tai Yang

Shaojun Wei

Leibo Liu

Shouyi Yin

Bo Liu

Kai Wang

Jiahao Wang

Haiyang Jiang

Jinjiang Yang

Xueting Cai

Weiwei Shan

Yang Yang

Weiguang Wang

Na Bai

Jingjing Guo

Xiaolan Cheng

Wei Bao

Xu Cheng

Tao Zhao

Qianqian Song

Bingqian Xu

Mengxiao Li

Guoqing He

Xuexiang Wang

Guoli Wei

Chunping Hu

Jingqing Hu

Xiaoning Wang

Jiege Huo

Xue Du

Jiao Chen

Handong Sun

Xiaoyan Sun

Jianxin Pu

Huaijiang Yan

Meng Cao

A method for predicting the fluctuation of circuit path delay on the basis of machine learning, comprising the following steps: S1: selecting suitable sample characteristics by means of analyzing the relationship between circuit characteristics and path delay; S2: generating a random path by means of enumerating values of randomized parameters, acquiring the maximum path delay by means of performing Monte Carlo simulation on the random path, selecting a reliable path by means of the 3σ standard, and using the sample characteristics and path delay of the reliable path as a sample set (D); S3: establishing a path delay prediction model, and adjusting parameters of the model; S4: verifying the precision and stability of the path delay prediction model; S5: obtaining the path delay. The method for predicting the fluctuation of circuit path delay on the basis of machine learning has the advantages of high precision and low running time, thereby having remarkable advantages in the accuracy and efficiency of timing analysis.

Method for predicting fluctuation of circuit path delay on basis of machine learning

A path delay prediction method for an integrated circuit based on feature selection and deep learning. First, an integrated feature selection method based on filter methods and wrapper methods is established to determine an optimal feature subset. Timing information and physical topological information of a circuit are then extracted to be used as input features of a model, and local physical and timing expressions of cells in circuit paths are captured by means of the convolution calculation mechanism of a convolutional neural network. In addition, a residual network is used to calibrate a path delay. Compared with traditional back-end design processes, the path delay prediction method provided by the invention has remarkable advantages in prediction accuracy and efficiency and has great significance in accelerating the integrated circuit design process.

Path delay prediction method for integrated circuit based on feature selection and deep learning

An optimization method for a digital integrated circuit is provided. Under the precondition of satisfying certain timing constraints, circuit-level, path-level and gate cell-level features of a circuit are extracted to construct a leakage power optimization model, and optimization data from commercial circuit optimization tools is used to train the model to predict voltage threshold types of gate cells after circuit optimization, such that the circuit can be optimized by adjusting voltage thresholds of gate cells in a post-routing gate-level netlist, thus realizing the optimization objective of reducing leakage power.

Optimization method for digital integrated circuit

A post-routing path delay prediction method for a digital integrated circuit is provided. First, physical design and static timing analysis are performed on a circuit by a commercial physical design tool and a static timing analysis tool, timing and physical information of a path is extracted before routing of the circuit to be used as input features of a prediction model, then the timing and physical correlation of all stages of cells in the path is captured by a transformer network, a predicted post-routing path delay is calibrated by a residual prediction structure, and finally, a final predicted post-routing path delay is output.

Post-routing path delay prediction method for digital integrated circuit

Disclosed in the present invention is a method for optimizing circuit timing based on a flexible register timing library. First, registers are simulated respectively in a case of a plurality of groups of an input signal conversion time, a clock signal conversion time, and a register load capacitance, corresponding actual propagation delays at this time are obtained by changing setup slack and hold slack of the registers, and actual propagation delays of the registers under specific input signal conversion time, clock signal conversion time, register load capacitances, setup slack, and hold slack are obtained through linear interpolation, to establish a flexible register timing library; and then static timing analysis is performed on all register paths in a circuit by using the library, a minimum clock cycle under a condition of satisfying that a setup time margin and a hold time margin are both greater than zero is found by changing the setup slack and hold slack of the registers, thereby improving the performance of the circuit without changing the design of the circuit and without increasing the area overheads of the circuit.

Method for optimizing circuit timing based on flexible register timing library

Disclosed in the present invention is a flexible modeling method for a timing constraint of a register. Simulation ranges of input terminal transition time, clock terminal transition time, and output load capacitance of a register are determined first, simulation is performed under each combination of input terminal transition time, clock terminal transition time, and output load capacitance to obtain a timing constraint range, then setup slack and hold slack are extracted in this constraint range with a particular interval, and then simulation is performed to obtain a clock terminal-to-output terminal delay. Finally, a mutually independent timing model of the register is established by using an artificial neural network, where the clock terminal-to-output terminal delay is modeled as a function of the input terminal transition time, the clock terminal transition time, the output load capacitance, the setup slack, the hold slack, and an output terminal state. A flexible timing constraint model in the present invention has advantages of low simulation overheads and high prediction precision, and is of great significance for static timing analysis timing signoff of a digital integrated circuit.

Flexible modeling method for timing constraint of register

Disclosed in the present invention is a method for predicting a delay at multiple corners for a digital integrated circuit, which is applicable to the problem of timing signoff at multiple corners. In the aspect of feature engineering, a path delay relationship at adjacent corners is extracted by using a dilated convolutional neural network (Dilated CNN), and learning is performed by using a bi-directional long short-term memory model (Bi-directional Long Short-Term Memory, BLSTM) to obtain topology information of a path. Finally, prediction results of a path delay at a plurality of corners are obtained by using an output of a multi-gate mixture-of-experts network model (Multi-gate Mixture-of-Experts, MMoE). Compared with a conventional machine learning method, the present invention can achieve prediction with higher precision through more effective feature engineering processing in a case of low simulation overheads, and is of great significance for timing signoff at multiple corners of a digital integrated circuit.

Method for predicting delay at multiple corners for digital integrated circuit

The invention discloses a ginseng-derived nanoparticle and a preparation method and application thereof. The ginseng-derived nanoparticle disclosed in the invention has a membrane structure, a particle size ranging from 150 to 500 nm and a peak particle size of 280 to 350 nm; and the ginseng-derived nanoparticle is prepared by multiple centrifugation, filtration and impurity removal. The ginseng-derived nanoparticle has good application prospects in developing drugs for preparing natural immunopotentiators and for preparing natural anti-tumor drugs.

Preparation and application of ginseng derived membranous microparticles

A compound of Formula I or pharmaceutically acceptable salt thereof and its preparation method and applications, the new structure of the compound of formula I has not been reported in literature. It is isolated fromvar.and can be a compound served as Trx1 selective inhibitor. The present invention further discloses a pharmaceutical composition, preparation of the compound of Formula I and its applications in preparing medicines for preventing or treating cancer. Iso A of the present invention has the advantages of low toxicity, high safety and strong pharmacological effect, which suggests a potential prospect in pharmaceutical applications.

[object Object]

A cache structure for use in implementing reconfigurable system configuration information storage, comprises: layered configuration information cache units: for use in caching configuration information that may be used by a certain or several reconfigurable arrays within a period of time; an off-chip memory interface module: for use in establishing communication; a configuration management unit: for use in managing a reconfiguration process of the reconfigurable arrays, in mapping each subtask in an algorithm application to a certain reconfigurable array, thus the reconfigurable array will, on the basis of the mapped subtask, load the corresponding configuration information to complete a function reconfiguration for the reconfigurable array. This increases the utilization efficiency of configuration information caches. Also provided is a method for managing the reconfigurable system configuration information caches, employing a mixed priority cache update method, and changing a mode for managing the configuration information caches in a conventional reconfigurable system, thus increasing the dynamic reconfiguration efficiency in a complex reconfigurable system.

Cache structure and management method for use in implementing reconfigurable system configuration information storage

Disclosed are a pre-decoding analysis-based configuration information cache management system, comprising a streaming media processing module, a configuration information prefetch FIFO module, a configuration information storage unit, and a cache controller module. Also disclosed is a management method for the pre-decoding analysis-based configuration information cache management system. The present invention allows for increased dynamic reconfiguration efficiency of a large-scale coarse-grained reconfigurable system.

Pre-decoding analysis based configuration information cache management method and system

The present invention discloses a pharmaceutical composition for treating cancer, comprising: (1) a herbal composition generated fromradix,radix,, andor an extract of the above mixed herbal medicine; (2) one or more chemotherapeutic compounds. The present invention also discloses use of the above pharmaceutical composition in the preparation of medicament for treating human cancer and in the preparation of medicament for reducing side effects of chemotherapeutic compounds in human body. The pharmaceutical composition of the present invention can reduce chemotherapy-induced peripheral neuropathic side effects such as limb paresthesia, pain, cold skin, formication, powerlessness and the like, increase tolerance dosages of anticancer drugs, and enhance efficacy of anticancer drugs.

Pharmaceutical composition for treating cancer and use thereof

The present invention discloses a Power-On-Reset (POR) circuit with zero steady-state current consumption and stable pull-up voltage. The POR circuit achieves zero steady-state current consumption during steady operation after the POR process by cutting off a power supply to a band-gap comparator circuit and a current comparator circuit after the POR process. The present invention has high reliability and stable pull-up voltage, is less susceptible to the impact of power-on rate of power supply, temperature, and process variation, has very low steady-state power consumption, and can be integrated in a SOC chip in low-power consumption applications.

Power-on-reset (POR) circuit with zero steady-state current consumption and stable pull-up voltage

Growing community of inventors

Jiangsu, China

Peng Cao