Arm Limited

Penaka Phani Goberu

Andy Wangkun Chen

Yew Keong Chong

Akash Bangalore Srinivasa

Amandeep Kaur

Khushal Gelda

Sreebin Sreedhar

Balaji Ravikumar

Vibin Vincent

Various implementations described herein are directed to a device having first circuitry with wordline drivers coupled to wordlines. The device may have second circuitry with switch structures that are coupled between a first voltage and ground. The switch structures may be configured to provide a second voltage to a power connection of each wordline driver based on the first voltage.

Wordline driver architecture

Various implementations described herein are related to a method for identifying multi-bank memory architecture having multiple banks including a first bank and a second bank. The method may receive a faulty row address having a faulty bank selection bit, and also, the method may select the first bank or the second bank for row redundancy operations based on the faulty bank selection bit.

Row redundancy techniques

Various implementations described herein are related to a device having memory circuitry with an array of bitcells coupled to a power rail. The device may have pulse-bias circuitry with stacks of transistors that are coupled to the power rail. In various instances, the stacks of transistors may be alternately activated so as to thereby provide a pulse-biased power supply to the array of bitcells via the power rail.

Memory architecture with pulsed-bias power

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Bengaluru, India

Penaka Phani Goberu