Synopsys, Inc.

Peivand Fallah-Tehrani

Nahmsuk Oh

Alireza Kasnavi

Subramanyam Sripada

Yansheng Luo

Jindrich Zejda

William Chiu-Ting Shu

Mahmoud Shahram

Alexander Gyure

Wenyuan Wang

Chi-Chong Lo

Seyed Alireza Kasnavi

Li Ding

Alireza Kasnavl

Shang-Woo Chyou

A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nominal values of channel length or metal width), to obtain at least a first value of the attribute. The method also uses a computationally inexpensive technique to estimate the same attribute, thereby to obtain at least a second value which is less accurate than the first value. Then the computationally inexpensive technique is repeatedly used on other values of the parameter(s), to obtain a number of additional second values of the attribute. Applying to the additional second values, a function obtained by calibrating the at least one second value to the at least one first value, can yield calibrated estimates very quickly, which represent the attribute's variation relatively accurately.

Determining a design attribute by estimation and by calibration of estimated value

A model for a circuit cell used in timing and signal integrity analysis in an integrated circuit design is automatically generated. A behavioral model, such as a gate current model is used in which the current in the circuit cell is determined as a function of the input voltage and the output voltage of the circuit cell as well as the history of at least one of the current, voltage, and charge values of the circuit cell. For example, the current in the circuit cell may be a function of the history of the current, which may be calculated incrementally using recursive convolution at each time step when using the model.

Modeling circuit cells for waveform propagation

Static timing and/or noise analysis are performed on a netlist of an integrated circuit, to estimate behavior of the netlist and to identify at least one violation by said behavior of a corresponding requirement thereon, such as setup time, hold time or bump height in a quiescent net. Thereafter, effect of engineering change order (ECO) to correct the violation are automatically analyzed, based on the layout, the parasitics, the timing and/or noise behavior, and the violation, followed by generation of a constraint on the behavior (called 'ECO' constraint), such as a timing constraint and/or a noise constraint. Next, the ECO constraint is automatically used, e.g. in a place and route tool, to select an ECO repair technique, from several ECO repair techniques that can overcome the violation. The selected ECO repair technique is automatically applied to the layout, to generate a modified layout which does not have the violation.

Generation of engineering change order (ECO) constraints for use in selecting ECO repair techniques

One embodiment of the invention provides a system that analyzes the propagation of noise through an integrated circuit. During operation, the system obtains an input noise signal to be applied to a cell within the integrated circuit. The system then looks up parameters specifying how noise affects the cell, and then uses the parameters to determine how the input noise signal affects the cell. This can involve determining if the input noise signal will cause the cell to fail and/or determining a propagated noise signal that emanates from the cell.

Method and apparatus for detecting and analyzing the propagation of noise through an integrated circuit

One embodiment of the invention provides a system that characterizes cells within an integrated circuit. During operation, the system obtains a number of input noise signals to be applied to the cell. The system then simulates responses of the cell to each of the input noise signals, and stores a representation of the responses. This allows a subsequent analysis operation to access the stored representation to determine a response of the cell instead of having to perform a time-consuming simulation operation.

Method and apparatus for characterizing the propagation of noise through a cell in an integrated circuit

A method for static timing analysis of deep sub-micron devices in presence of crosstalk. The present invention provides an efficient platform for fast and accurate static timing verification of large scale transistor and cell level netlists, with coupled interconnects and high switching speeds. The present invention also provides a novel approach to solve the coupled noise problem in static timing verification. The present invention also provides for a method of determining worst case aggressor switching time for a cross-coupled interconnect stage. After the worst case aggressor switching time is determined, the netlist is then resimulated using the worst case aggressor switching time to determine more accuate stage delay and slew of the interconnect stage. The output waveform is recorded and utilized as the input of subsequent stages.

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Camarillo, CA, United States of America

Peivand Fallah-Tehrani