Freescale Semiconductor,inc.

Nxp Usa, Inc.

Peilin Wang

Edouard D De Fresart

Jingjing Chen

Ganming Qin

Edouard De Frésart

Wenyi Li

Pon Sung Ku

Hongwei Zhou

D Defresart Edouard

Embodiments of semiconductor devices and methods of their formation include providing a semiconductor substrate having a top surface, a bottom surface, an active region, and an edge region, and forming a gate structure in a first trench in the active region of the semiconductor substrate. A termination structure is formed in a second trench in the edge region of the semiconductor substrate. The termination structure has an active region facing side and a device perimeter facing side. The method further includes forming first and second source regions of the first conductivity type are formed in the semiconductor substrate adjacent both sides of the gate structure. A third source region is formed in the semiconductor substrate adjacent the active region facing side of the termination structure. The semiconductor device may be a trench metal oxide semiconductor device, for example.

Methods of manufacturing trench semiconductor devices with edge termination structures

A power MOSFET has a main-FET (MFET) and an embedded current sensing-FET (SFET). MFET gate runners are coupled to SFET gate runners by isolation gate runners (IGRs) in a buffer space between the MFET and the SFET. In one embodiment, n IGRs (i=1 to n) couple n+1 gates of a first portion of the MFET () to n gates of the SFET. The IGRs have zigzagged central portions where each SFET gate runner is coupled via the IGRs to two MFET gate runners. The zigzagged central portions provide barriers that block parasitic leakage paths, between sources of the SFET and sources of the MFET, for all IGRs except the outboard sides of the first and last IGRs. These may be blocked by increasing the body doping in regions surrounding the remaining leakage paths. The IGRs have substantially no source regions.

Power MOSFET current sense structure and method

Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure () includes a trench gate structure (), a lateral gate structure (), a body region () having a first conductivity type, a drain region () and first and second source regions () having a second conductivity type. The first and second source regions () are formed within the body region (). The drain region () is adjacent to the body region () and the first source region () is adjacent to the trench gate structure (), wherein a first portion of the body region () disposed between the first source region () and the drain region () is adjacent to the trench gate structure (). A second portion of the body region () is disposed between the second source region () and the drain region (), and the lateral gate structure () is disposed overlying the second portion of the body region ().

Semiconductor device and related fabrication methods

A power MOSFET includes a semiconductor substrate with an upper surface, a cavity of a first depth in the substrate whose sidewall extends to the upper surface, a dielectric liner in the cavity, a gate conductor within the dielectric liner extending to or above the upper surface, body region(s) within the substrate of a second depth, separated from the gate conductor in a lower cavity region by first portion(s) of the dielectric liner of a first thickness, and source region(s) within the body region(s) extending to a third depth that is less than the second depth. The source region(s) are separated from the gate conductor by a second portion of the dielectric liner of a second thickness at least in part greater than the first thickness. The dielectric liner has a protrusion extending laterally into the gate conductor away from the body region(s) at or less than the third depth.

Power MOSFET structure and method

A high voltage vertical field effect transistor device () is fabricated in a substrate () using angled implantations () into trench sidewalls formed above recessed gate poly layers () to form self-aligned N+ regions () adjacent to the trenches and along an upper region of an elevated substrate. With a trench fill insulator layer () formed over the recessed gate poly layers (), self-aligned P+ body contact regions () are implanted into the elevated substrate without counter-doping the self-aligned N+ regions (), and a subsequent recess etch removes the elevated substrate, leaving self-aligned N+ source regions (-) and P+ body contact regions (-).

Trench FET with source recess etch

A TMOS device () is formed using a semiconductor layer () of a first type. First and second regions () of the second type are formed in the semiconductor layer and are spaced apart. A third region () is formed in the semiconductor layer by implanting. The third region is between and contacts the first and second doped regions, is of the second conductivity type, and is less heavily doped than the first and second doped regions. A gate stack () is formed over a portion of the first doped region, a portion of the second doped region, and the third doped region. By implanting after forming the gate stack, fourth and fifth regions () of the first type are formed in interior portions of the first and second doped regions, respectively. The third region being of the same conductivity type as the first and second regions reduces Miller capacitance.

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Beijing, China

Peilin Wang