Texas Instruments Corporation

Asm America, Inc.

Interuniversitair Micro-elektronica Centrum Vzw

Peijun Chen

Amitabh Jain

Duofeng Yue

Sue E Crank

Thomas Dyer Bonifield

Homi C Mogul

Noel M Russell

Douglas E Mercer

Robert M Wallace

Jorge Adrian Kittl

Doufeng Yue

Jan Willem Maes

Jiong-Ping Lu

Deborah J Riley

Trace Quentin Hurd

Steven A Henck

S Charles Baber

Shirin Siddiqui

Mathieu Caymax

Tsai Wilman

Jie-Jie Xu

According to one embodiment of the invention, a method for nickel silicidation includes providing a substrate having a source region, a gate region, and a drain region, forming a source in the source region and a drain in the drain region, annealing the source and the drain, implanting, after the annealing the source and the drain, a heavy ion in the source region and the drain region, depositing a nickel layer in each of the source and drain regions, and heating the substrate to form a nickel silicide region in each of the source and drain regions by heating the substrate.

Method and system for improved nickel silicide

The present invention provides a method of manufacturing a metal silicide electrode () for a semiconductor device (). The method comprises depositing by physical vapor deposition, germanium atoms () and transition metal atoms () to form a metal-germanium alloy layer () on a semiconductor substrate (). The metal-germanium alloy layer and the semiconductor substrate are reacted to form a metal silicide electrode. Other aspects of the present invention include a method of manufacturing an integrated circuit ().

Metal-germanium physical vapor deposition for semiconductor device defect reduction

The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a gate dielectric layer and gate electrode layer. The semiconductor device may further include source/drain regions located in/over the substrate and adjacent the gate structure, and a nickel alloy silicide located in the source/drain regions, the nickel alloy silicide having an amount of indium located therein.

Nickel alloy silicide including indium and a method of manufacture therefor

The present invention provides a method for fabricating a dielectric stack in an integrated circuit comprising the steps of (i) forming a high-k dielectric layer on a semiconductor substrate, (ii) subjecting the semiconductor substrate with the high-k dielectric layer to a nitrogen comprising vapor phase reactant and silicon comprising vapor phase reactant in a plasma-enhanced chemical vapor deposition process (PECVD) or a plasma-enhanced atomic layer chemical vapor deposition (PE ALCVD) process. Furthermore, the present invention provides a dielectric stack in an integrated circuit comprising (i) a high-k dielectric layer comprising at least a high-k material, (ii) a dielectric layer comprising at least silicon and nitrogen; (iii) an intermediate layer disposed between the high-k dielectric layer and the dielectric layer, the intermediate layer comprising the high-k material, silicon, and nitrogen.

Method for forming a high-k dielectric stack

The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (), as well as a nickel silicide region () located over the substrate (), the nickel silicide region () having an amount of indium located therein.

Nickel silicide including indium and a method of manufacture therefor

The present invention provides a method of manufacturing a metal silicide electrode () for a semiconductor device (). The method comprises depositing by physical vapor deposition, halogen atoms () and transition metal atoms () to form a halogen-containing metal layer () on a semiconductor substrate (). The halogen-containing metal layer and the semiconductor substrate are reacted to form a metal silicide electrode. Other aspects of the present invention include a method of manufacturing an integrated circuit () comprising the metal silicide electrode.

Metal-halogen physical vapor deposition for semiconductor device defect reduction

The present invention provides a method of manufacturing a metal silicide electrode () for a semiconductor device (). The method comprises implanting small atoms into an nMOS semiconductor substrate () to a depth () no greater than about 30 nanometers into the nMOS semiconductor substrate. The method further comprises depositing a transition metal layer () over the nMOS semiconductor substrate. The transition metal layer and the nMOS semiconductor substrate are reacted to form the metal silicide electrode. Other aspects of the present invention include a method of manufacturing an integrated circuit ().

Metal silicide induced lateral excessive encroachment reduction by silicon &#x3c;110&#x3e; channel stuffing

A method of preparing a die comprises treating exposed silicon to form an oxide prior to silicide formation; and depositing metal on the oxide. The metal may comprise titanium, cobalt, nickel, platinum, palladium, tungsten, molybdenum, or combinations thereof on the oxide. The oxide may be less than or equal to about 15 angstroms thick. In various embodiments, treating exposed silicon to form an oxide comprises forming a non-thermal oxide. Treating exposed silicon to form an oxide may also comprise treating the exposed silicon with an oxidizing plasma; alternatively, treating exposed silicon to form an oxide may comprise forming a chemical oxide. In certain other embodiments, treating exposed silicon to form an oxide comprises treating exposed silicon with a solution comprising ammonium hydroxide, hydrogen peroxide, and water; hydrochloric acid, hydrogen peroxide, and water; hydrogen peroxide; ozone; ozonated deionized water; or combinations thereof.

Treatment of silicon prior to nickel silicide formation

Channel-hot-carrier reliability can be improved by deuterium passivation of the gate interface. By performing high temperature steps (above 300 degrees Celsius) in a deuterium-containing ambient, harmful depletion of deuterium due to diffusion away from the gate interface is avoided.

Semiconductor process with deuterium predominance at high temperature

An integrated circuit fabrication process in which residual fluorine contamination on metal surfaces after ashing is removed by exposure to an NH.sub.3 /O.sub.2 plasma.

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Dallas, TX, United States of America

Peijun Chen