International Business Machines Corporation

Kabushiki Kaisha Toshiba

Sony Computer Entertainment Inc.

Toshiba America Electronic Components, Inc.

Peichun Peter Liu

Charles Ray Johns

Thuong Quang Truong

Rajinder Paul Singh

Michael Norman Day

James Allan Kahle

Jieming Qi

David Mui

Shigehiro Asano

David John Krolak

Dwain Alan Hicks

Michael John Mayfield

Alvan Wing Ng

Takeshi Yamazaki

Matthew Edward King

Brian D Branson

Shih-Hsiung Steve Tung

Sang Hoo Dhong

Harm Peter Hofstee

David James Shippy

Todd Swanson

Hung Qui Le

Balaram Sinharoy

Manoj N Kumar

David William Boerstler

Christopher Hans Olson

George McNeil Lattimore

Ronald P Hall

Wen-Tzer Thomas Chen, Jr

Paul Allen Ganfield

Robert J Reese

Hoichi Cheong

Yuji Suzuki

Jonathan James DeMent

Kent Harold Haselhorst

Glen Howard Handlogten

Shih-Hsiung Stephen Tung

Francis Patrick O'Connell

John Samuel Liberty

Salim Ahmed Shah

Robert Greg McDonald

Song C Kim

Tsutomu Horikawa

Kin Shing Chan

Takashi Omizo

Shohji Onishi

Scott Raymond Cottier

Huy Van Pham

Kevin C Stelzer

Victor Shadan

Asano Shigehiro

Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.

Controlling bandwidth reservations method and apparatus

A design structure for a livelock resolution circuit is provided. When a bus unit detects a timeout condition, or potential timeout condition, the bus unit activates a livelock resolution request signal. A livelock resolution unit receives livelock resolution requests from the bus units and signals an attention to a control processor. The control processor performs actions to attempt to resolve the livelock condition. Once a bus unit that issued a livelock resolution request has managed to successfully issue its command, it deactivates its livelock resolution request. If all livelock resolution request signals are deactivated, then the control processor instructs the bus and all bus units to resume normal activity. On the other hand, if the control processor determines that a predetermined amount of time passes without any progress being made, it determines that a hang condition has occurred.

Structure for a livelock resolution circuit

A system for communicating command parameters between a processor and a memory flow controller is provided. The system makes use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power 'stall' state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

System for communicating command parameters between a processor and a memory flow controller

A mechanism is provided for resolving livelock conditions in a multiple processor data processing system. When a bus unit detects a timeout condition, or potential timeout condition, the bus unit activates a livelock resolution request signal. A livelock resolution unit receives livelock resolution requests from the bus units and signals an attention to a control processor. The control processor performs actions to attempt to resolve the livelock condition. Once a bus unit that issued a livelock resolution request has managed to successfully issue its command, it deactivates its livelock resolution request. If all livelock resolution request signals are deactivated, then the control processor instructs the bus and all bus units to resume normal activity. On the other hand, if the control processor determines that a predetermined amount of time passes without any progress being made, it determines that a hang condition has occurred.

Livelock resolution

The present invention provides a method and apparatus for creating memory barriers in a Direct Memory Access (DMA) device. A memory barrier command is received and a memory command is received. The memory command is executed based on the memory barrier command. A bus operation is initiated based on the memory barrier command. A bus operation acknowledgment is received based on the bus operation. The memory barrier command is executed based on the bus operation acknowledgment. In a particular aspect, memory barrier commands are direct memory access sync (dmasync) and direct memory access enforce in-order execution of input/output (dmaeieio) commands.

Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment

Methods and apparatus provide for transferring a plurality of data blocks between a shared memory and a local memory of a processor in response to a single DMA command issued by the processor to a direct memory access controller (DMAC), wherein the processor is capable of operative communication with the shared memory and the DMAC is operatively coupled to the local memory.

Methods and apparatus for list transfers using DMA transfers in a multi-processor system

The present invention provides a method and a system for providing cache management commands in a system supporting a DMA mechanism and caches. A DMA mechanism is set up by a processor. Software running on the processor generates cache management commands. The DMA mechanism carries out the commands, thereby enabling the software program management of the caches. The commands include commands for writing data to the cache, loading data from the cache, and for marking data in the cache as no longer needed. The cache can be a system cache or a DMA cache.

Method to provide cache management commands for a DMA controller

Systems and methods for efficiently switching context between processing elements are disclosed. These systems and methods may transfer the context of a processing element to a storage location. Using the DMA controller of a target processing element, the contents of this storage location may be transferred to another storage location associated with the target processing element. The context may then be restored from this storage location to the proper locations in the target processing element, and the target processing element may then begin processing utilizing this transferred context.

Method and system for efficient context swapping

Livelock resolution method

A system and method for communicating command parameters between a processor and a memory flow controller are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power 'stall' state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

System and method for communicating command parameters between a processor and a memory flow controller

A method, an apparatus, and a computer program product are provided for the handling of write mask operations in an XDR&#x2122; DRAM memory system. This invention eliminates the need for a two-port array because the mask generation is done as the data is received. Less logic is needed for the mask calculation because only 144 of the 256 possible byte values are decoded. The mask value is generated and stored in a mask array. Independently, the write data is stored in a write buffer. The mask value is utilized to generate a write mask command. Once the write mask command is issued, the write data and the mask value are transmitted to a multiplexer. The multiplexer masks the write data using the mask value, so that the masked data can be stored in the XDR DRAMS.

Method and apparatus for generating a mask value and command for extreme data rate memories utilizing error correction codes

A method, an apparatus, and a computer program are provided for controlling memory access. Direct Memory Access (DMA) units have become commonplace in a number of bus architectures. However, managing limited system resources has become a challenge with multiple DMA units. In order to mange the multitude of commands generated and preserve dependencies, embedded flags in commands or a barrier command are used. These operations then can control the order in which commands are executed so as to preserve dependencies.

Establishing command order in an out of order DMA command queue

A method and apparatus are provided for efficiently operating a round robin arbitration system in a given computer system. The system utilizes a series of banks of requestors and pointer. The banks of requestors and pointers operate on sequential AND-OR-Inverter/OR-AND-Inverter (AOI/OAI) logic to advance the pointer and efficiently select those requestors with pending requests. The use of the AOI/OAI logic circuitry in the banks of requestors and pointers allows for efficient selection and minimization of complex circuitry reducing the overall circuit area.

Round robin selection logic improves area efficiency and circuit speed

A system and method are provided for setting up a direct memory access for a first processor. The system includes the first processor and a local memory. The local memory is coupled to the first processor. A first direct memory access controller (DMAC) is coupled to the first processor and the local memory. A system memory is in communication with the first DMAC. A second processor is in communication with the first DMAC such that the second processor sets up the first DMAC to handle data transfer between the local memory and the system memory. The second processor is interrupted when the first DMAC finishes handling the data transfer.

Proxy direct memory access

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Austin, TX, United States of America

Peichun Peter Liu