Xilinx, Inc.

Falcon Computing

Peichen Pan

Peng Zhang

Xuechao Wei

Cody Hao Yu

Kecheng Hao

Chang'an Ye

Systems and methods for automated systolic array design from a high-level program are disclosed. One implementation of a systolic array design supporting a convolutional neural network includes a two-dimensional array of reconfigurable processing elements arranged in rows and columns. Each processing element has an associated SIMD vector and is connected through a local connection to at least one other processing element. An input feature map buffer having a double buffer is configured to store input feature maps, and an interconnect system is configured to pass data to neighboring processing elements in accordance with a processing element scheduler. A CNN computation is mapped onto the two-dimensional array of reconfigurable processing elements using an automated system configured to determine suitable reconfigurable processing element parameters.

Systems and methods for systolic array design from a high-level program

An embodiment of a method of high-level synthesis of a dataflow pipeline is disclosed. This embodiment includes obtaining processes from the high-level synthesis of the dataflow pipeline. A schedule for read operations and write operations for first-in, first-out data channels of the processes is determined. A dataflow through the dataflow pipeline for the schedule is determined. An edge-weighted directed acyclic graph for the processes and the dataflow is generated. A longest path in the edge-weighted directed acyclic graph is located. A weight for the longest path is output as an estimate, such as a latency estimate for example, for the dataflow.

Dataflow parameter estimation for a design

Growing community of inventors

San Jose, CA, United States of America

Peichen Pan