Taiwan Semiconductor Manufacturing Comp. Ltd.

Dell Products Inc.

National Yang Ming Chiao Tung University

Pei-Yu Wang

Chih-Hao Wang

Ching-Wei Tsai

Huan-Chieh Su

Chun-Yuan Chen

Kuan-Lun Cheng

Cheng-Chi Chuang

Yu-Xuan Huang

Sai-Hooi Yeong

Wei Ju Lee

Chia-Hao Chang

Li-Zhen Yu

Cheng-Ting Chung

Yi-Hsun Chiu

Zhi-Chang Lin

Chun-Hsiung Lin

Wai-Yi Lien

Min Cao

Chih-Chao Chou

Li-Yang Chuang

Chi On Chui

Hou-Yu Chen

Shang-Wen Chang

Pei-Hsun Wang

Kai-Chieh Yang

Yi-Bo Liao

Yu-Ming Lin

Shih-Chuan Chiu

Kuo-Cheng Chiang

Kuan-Ting Pan

Kuan-lun Cheng

Bing-Yue Tsui

Chih-Chung Lin

Chung-Wei Wang

You-Liang Chen

A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.

Method and device for boosting performance of FinFETs via strained spacer

An IC structure includes a first transistor, first gate spacers, a second transistor, second gate spacers, a backside metal line, and a metal contact. The first transistor includes first source/drain regions and a first gate structure between the first source/drain regions. The first gate spacers space apart the first source/drain regions from the first gate structure. The second transistor comprises second source/drain regions and a second gate structure between the second source/drain regions. The second gate spacers space apart the second source/drain regions from the second gate structure. The first gate spacers and the second gate spacers extend along a first direction. The backside metal line extends between the first transistor and the second transistor along a second direction. The first metal contact wraps around one of the second source/drain regions and has a protrusion interfacing the backside metal line.

Integrated circuit structure with backside via rail

A method of fabricating a semiconductor device includes providing a dummy structure including channel layers disposed over a frontside of a substrate, inner spacers disposed between adjacent channels of the channel layers and at lateral ends of the channel layers, and a gate structure interposing the plurality of channel layers. The dummy structure is disposed at an active edge adjacent to an active region. Perform an etching process to etch the gate structure and the plurality of channel layers to form a cut region along the active edge. Deposit a conductive material in the cut region to form a conductive feature. The method further includes thinning the substrate from a backside of the substrate to expose the conductive feature and forming a backside metal wiring layer on the backside of the substrate. The backside metal wiring layer is in electrical connection with the conductive feature.

Semiconductor device with backside power rail

A semiconductor device including an embedded channel structure, a sidewall channel structure and a gate electrode structure is provided. The embedded channel structure is disposed on a substrate. The sidewall channel structure is disposed on the substrate, and located at a lateral side of the embedded channel structure. The gate electrode structure is disposed on the substrate, encircles the embedded channel structure and is located between the embedded channel structure and the sidewall channel structure.

Semiconductor device and method of fabricating a semiconductor device

In an embodiment, a device includes: a first fin; a gate structure over the first fin; a first source/drain region adjacent the gate structure; an etch stop layer over the first source/drain region; a conductive line over the etch stop layer, the conductive line isolated from the first source/drain region by the etch stop layer, a top surface of the conductive line being coplanar with a top surface of the gate structure; and a power rail contact extending through the first fin, the power rail contact connected to the first source/drain region.

Semiconductor devices

The present disclosure relates to a semiconductor device having a backside source/drain contact, and method for forming the device. The semiconductor device includes a source/drain feature having a top surface and a bottom surface, a first silicide layer formed in contact with the top surface of the source/drain feature, a first conductive feature formed on the first silicide layer, and a second conductive feature having a body portion and a first sidewall portion extending from the body portion, wherein the body portion is below the bottom surface of the source/drain feature, and the first sidewall portion is in contact with the first conductive feature.

Semiconductor devices with backside power rail and methods of fabrication thereof

A semiconductor device includes a first fin protruding upwardly from a substrate, a second fin protruding upwardly from the substrate, a first gate structure having a first portion that at least partially wraps around an upper portion of the first fin and a second portion that at least partially wraps around an upper portion of the second fin, a second gate structure having a portion that at least partially wraps around the upper portion of the first fin, and a dielectric feature having a first portion between the first and second portions of the first gate structure. In a lengthwise direction of the first fin, the dielectric feature has a second portion extending to a sidewall of the second gate structure.

Method for metal gate cut and structure thereof

The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench, depositing a first ferroelectric layer over the interfacial layer, removing the first ferroelectric layer from the nFET structure, depositing a metal oxide layer in each gate trench, depositing a second ferroelectric layer over the metal oxide layer, removing the second ferroelectric layer from the pFET structure, and depositing a gate electrode in each gate trench.

Metal oxide interlayer structure for NFET and PFET

A semiconductor device includes a substrate, nanostructures vertically suspended above the substrate, a metal gate structure wrapping each of the nanostructures, an epitaxial feature having a first sidewall in physical contact with end portions of the nanostructures, and an air gap disposed between the epitaxial feature and the metal gate structure. The air gap exposes the first sidewall of the epitaxial feature and the end portions of the nanostructures.

Multi-gate device with air gap spacer and fabrication methods thereof

In an embodiment, a device includes: a first nanostructure over a substrate, the first nanostructure including a channel region and a first lightly doped source/drain region, the first lightly doped source/drain region adjacent the channel region; a first epitaxial source/drain region wrapped around four sides of the first lightly doped source/drain region; an interlayer dielectric over the first epitaxial source/drain region; a source/drain contact extending through the interlayer dielectric, the source/drain contact wrapped around four sides of the first epitaxial source/drain region; and a gate stack adjacent the source/drain contact and the first epitaxial source/drain region, the gate stack wrapped around four sides of the channel region.

An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, an epitaxial regrowth layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is over a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is over a backside of the source epitaxial structure and a backside of the drain epitaxial structure. The epitaxial regrowth layer is on the backside of a first one of the source epitaxial structure and the drain epitaxial structure. The backside via extends through the backside dielectric layer and overlaps the epitaxial regrowth layer.

Integrated circuit structure with backside via

A device includes a first semiconductor strip protruding from a substrate, a second semiconductor strip protruding from the substrate, an isolation material surrounding the first semiconductor strip and the second semiconductor strip, a nanosheet structure over the first semiconductor strip, wherein the nanosheet structure is separated from the first semiconductor strip by a first gate structure including a gate electrode material, wherein the first gate structure partially surrounds the nanosheet structure, and a first semiconductor channel region and a semiconductor second channel region over the second semiconductor strip, wherein the first semiconductor channel region is separated from the second semiconductor channel region by a second gate structure including the gate electrode material, wherein the second gate structure extends on a top surface of the second semiconductor strip.

Hybrid channel semiconductor device and method

In an embodiment, a device includes: a first interconnect structure including metallization patterns; a second interconnect structure including a power rail; a device layer between the first interconnect structure and the second interconnect structure, the device layer including a first transistor, the first transistor including an epitaxial source/drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization patterns, the conductive via contacting the epitaxial source/drain region.

A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.

Growing community of inventors

Hsinchu, Taiwan

Pei-Yu Wang