Industrial Technology Research Institute

National Central University

Pei-Wen Luo

Wen-Ching Wu

Ding-Ming Kwai

Yeong-Jar Chang

Ji-Jan Chen

Cheng-Wen Wu

Chin-Long Wey

Jung-Chi Ho

Liang-Chia Cheng

Hsiu-Chuan Shih

Jwu-E Chen

Chi-Kang Chen

A memory system comprises a memory controller and a memory device having one or more memory ranks and multiple memory electrically connected to the one or more memory ranks. The memory controller includes at least one analysis module and at least one switching determination module. The analysis module analyzes states of multiple memory control commands corresponding to a particular memory rank to generate a control parameter. The switching determination module determines whether at least one switching command is sent according to the control parameter, a current operation mode of the particular memory rank, and an operation state of the particular memory rank. When the memory device receives a first switching command of the at least one command, the particular rank and at least one part of the memory internal circuits are switched from the normal voltage operation mode to the low voltage operation mode.

Memory controlling method and memory system

A yield evaluating apparatus and a method thereof are provided. The yield evaluating apparatus includes a spatial correlation module. The spatial correlation module receives at least one process-related data and a plurality of circuit layouts and obtains a correlation coefficient between unit elements in the circuit layouts according to the process-related data. The spatial correlation module calculates a spatial correlation between elements in each of the circuit layouts according to the correlation coefficient and selects one of the circuit layouts according to the spatial correlations.

Yield evaluating apparatus and method thereof

IC with built-in self-test and design method thereof. The IC comprises an SD-ADC and a Dft circuit. The Dft circuit uses a digital stimulus signal to solve the deadlock problem of the on-chip analog testing and avoid thermal noise. Moreover, according to the design method of the IC, circuits having different specification can use the Dft circuit without performance degradation for original SD-ADC.

IC with built-in self-test and design method thereof

Growing community of inventors

Kaohsiung, Taiwan

Pei-Wen Luo