Taiwan Semiconductor Manufacturing Comp. Ltd.

Pei-Shiang Chen

Jeng-Horng Chen

Hung-Chun Wang

Cheng-Hung Chen

Shih-Chi Wang

Ru-Gun Liu

Wen-Chun Huang

Tzu-Chin Lin

Nian-Fuh Cheng

Faruk Krecinic

Chia-Chi Lin

The present disclosure provides for many different embodiments of a charged particle beam data storage system and method. In an example, a method includes dividing a design layout into a plurality of units; creating a lookup table that maps each of the plurality of units to its position within the design layout and a data set, wherein the lookup table associates any repeating units in the plurality of units to a same data set; and exposing an energy sensitive layer to a charged particle beam based on the lookup table.

Electron beam data storage system and method for high volume manufacturing

The present disclosure provides a method for electron-beam (e-beam) lithography patterning. The method includes forming a resist layer on a substrate; performing a first e-beam exposure process to the resist layer according to a first pattern; performing a second e-beam exposure process to the resist layer according to a second pattern, wherein the second patterned is overlapped to the first pattern on the resist layer; and developing the resist layer.

Method and system for E-beam lithography with multi-exposure

The present disclosure provides a method of improving a layer to layer overlay error by an electron beam lithography system. The method includes generating a smart boundary of two subfields at the first pattern layer and obeying the smart boundary at all consecutive pattern layers. The same subfield is exposed by the same electron beam writer at all pattern layers. The overlay error caused by the different electron beam at different layer is improved.

Smart subfield method for E-beam lithography

The present disclosure provides a dithering method of increasing wafer throughput by an electron beam lithography system. The dithering method generates an edge map from a vertex map. The vertex map is generated from an integrated circuit design layout (such as an original pattern bitmap). A gray map (also referred to as a pattern gray map) is also generated from the integrated circuit design layout. By combining the edge map with the gray map, a modified integrated circuit design layout (modified pattern bitmap) is generated for use by the electron beam lithography system.

Data process for E-beam lithography

Provided is a method of performing a maskless lithography process. The method includes providing a proximity correction pattern. The method includes generating a deformed pattern based on the proximity correction pattern. The method includes performing a first convolution process to the proximity correction pattern to generate a first proximity correction pattern contour. The method includes processing the first proximity correction pattern contour to generate a second proximity correction pattern contour. The method includes performing a second convolution process to the deformed pattern to generate a first deformed pattern contour. The method includes processing the first deformed pattern contour to generate a second deformed pattern contour. The method includes identifying mismatches between the second proximity correction pattern contour and the second deformed pattern contour. The method includes determining whether the deformed pattern is lithography-ready in response to the identifying.

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Hsinchu, Taiwan

Pei-Shiang Chen