Au Optronics Corporation

Pei-Ming Chen

Wei-Ming Huang

Chun-Hsiun Chen

Chuan-Sheng Wei

Chang-Yu Huang

Chih-Hung Shih

Ming-Yao Chen

Sheng-Wen Huang

Wen-Yi Hsu

Guang-Ren Shen

Zeng-De Chen

Sheng-Chao Liu

Maw-Song Chen

Shin-Shueh Chen

Te-Chun Huang

Hsun-Chen Chu

A touch apparatus includes a substrate, a plurality of pixel structures, a first touch electrode, a second touch electrode, a third touch electrode and a first conductive pattern. The first touch electrode and the second touch electrode are located at a first side of a transparent window. The third touch electrode is located at a second side of the transparent window. The first touch electrode, the second touch electrode and the third touch electrode are sequentially arranged in a first direction. A main portion of the first conductive pattern is electrically connected to the first touch electrode. The main portion of the first conductive pattern overlaps with the second touch electrode and is electrically isolated from the second touch electrode. A dummy portion of the first conductive pattern is electrically connected to the third touch electrode and structurally separated from the main portion of the first conductive pattern.

Touch apparatus

A touch display panel is provided, including a common electrode ring, a first and a second common electrode pattern, pixel structures, an edge common signal line, and common signal lines disposed on a substrate. The first and second common electrode patterns and the pixel structures are located in a region surrounded by the common electrode ring. The first common electrode pattern is spaced from the second common electrode pattern by a gap. The first and the second common electrode patterns respectively overlap some of the pixel structures. The edge common signal line is disposed on the substrate, traces along the gap, and extends toward the common electrode ring to be electrically connected to the common electrode ring. The first common electrode pattern overlaps and is electrically connected to one common signal line. The second common electrode pattern overlaps and is electrically connected to another common signal line.

Touch display panel

A manufacturing method of an array substrate including following steps is provided. A plurality of scan lines are formed on a substrate having a pixel region and a fan-out region. A plurality of data lines are formed. A plurality of transistors are formed and respectively electrically connected to the corresponding scan lines and data lines. A plurality of common electrodes are formed. A plurality of pixel electrodes are formed and respectively electrically connected to the corresponding transistors. A plurality of first fan-out lines, second fan-out lines, and third fan-out lines are formed in the fan-out region. Each of the third fan-out lines includes a transparent conductive layer and an auxiliary conductive layer located on and contacting the transparent conductive layer. The third fan-out lines and the common electrodes are formed by the same photomask.

Manufacturing method of array substrate

An active device includes a poly-silicon semiconductor layer, a first insulating layer, a gate electrode, a second insulating layer, a first through hole, an oxide semiconductor layer, a first electrode and a second electrode. The poly-silicon semiconductor layer includes a first doped region, a channel region and a second doped region. The gate electrode is disposed on the first insulating layer covering the poly-silicon semiconductor layer, and corresponds to the channel region. The gate electrode is covered by the second insulating layer, where the first and second insulating layers have a first through hole. The oxide semiconductor layer is disposed on the second insulating layer and corresponds to the gate electrode. The first and second electrodes are oppositely disposed on the oxide semiconductor layer. The oxide semiconductor layer is electrically connected to the second electrode, and to the second doped region via the first through hole.

Active device

An integration method of fabricating optical sensor device and thin film transistor device includes the follow steps. A substrate is provided, and a gate electrode and a bottom electrode are formed on the substrate. A first insulating layer is formed on the gate electrode and the bottom electrode, and the first insulating layer at least partially exposes the bottom electrode. An optical sensing pattern is formed on the bottom electrode. A patterned transparent semiconductor layer is formed on the first insulating layer, wherein the patterned transparent semiconductor layer includes a first transparent semiconductor pattern covering the gate electrode, and a second transparent semiconductor pattern covering the optical sensing pattern. A source electrode and a drain electrode are formed on the first transparent semiconductor pattern. A modification process including introducing at least one gas is performed on the second transparent semiconductor pattern to transfer the second transparent semiconductor pattern into a conductive transparent top electrode.

Method of fabricating optical sensor device and thin film transistor device

An array substrate includes a substrate and a plurality of pixel structures. At least one pixel structure includes a gate electrode, a gate insulating layer, a source electrode and a drain electrode, a patterned semiconductor layer, a first passivation layer, and a transparent conductive pattern disposed in a pixel region of the substrate. The patterned semiconductor layer includes a first semiconductor pattern and a second semiconductor pattern. The first semiconductor pattern substantially corresponds to the gate electrode and covers a portion of the source electrode and a portion of the drain electrode. The second semiconductor pattern covers a portion of the drain electrode. The first passivation layer is disposed on the patterned semiconductor layer and has a first opening exposing a portion of the second semiconductor pattern. The transparent conductive pattern is disposed on the first passivation layer and electrically connected to the second semiconductor pattern through the first opening.

Array substrate

A manufacturing method of an array substrate includes the following steps. A substrate having pixel region and a peripheral region is provided. A plurality of pixel structures are formed in the pixel region, wherein at least one of the pixel structures is formed by the following steps. A gate electrode, a gate insulating layer, and a source electrode and a drain electrode are formed. A patterned semiconductor layer including a first semiconductor pattern and a second semiconductor pattern is formed. The second semiconductor pattern covers a portion of the drain electrode. A first passivation layer is formed. The first passivation layer has a first opening exposing a portion of the second semiconductor pattern. A transparent conductive pattern is formed on the first passivation layer, and the transparent conductive pattern is electrically connected to the second semiconductor pattern through the first opening.

Array substrate and manufacturing method thereof

A pixel structure and its fabrication method are provided. The pixel structure includes a channel layer, a first patterned metal layer, a first insulation layer, a second patterned metal layer, a second insulation layer, and a pixel electrode. The first patterned metal layer includes a data line, a source, and a drain. The first insulation layer has a first opening exposing the drain. The second patterned metal layer includes a scan line and a capacitor electrode. The capacitor electrode has at least one first portion overlapping the data line. The second insulation layer has a second opening communicating with the first opening to expose the drain. The pixel electrode is connected to the drain through the first opening and the second opening and at least overlaps the first portion of the capacitor electrode.

Pixel structure and fabrication method of pixel structure

An electrophoretic display with threshold voltage drift compensation functionality includes a gate driving circuit, a data driving circuit, a controller and a pixel array. The gate driving circuit provides plural gate signals according to a scan control signal. The data driving circuit provides plural data signals according to a data control signal. The controller is employed to provide the scan control signal and the data control signal. The pixel array is utilized for displaying images according to the gate signals and the data signals. Each of the gate signals includes a writing enable pulse for enabling write operations of the data signals during a writing period. And during a compensation period, each of the gate signals includes a compensation pulse for performing threshold voltage drift compensation operations on the data switches of the pixel array, and the data signals are set to hold a common voltage.

Electrophoretic display and method of driving the same

A master having a substrate including displaying units and an ESD protection structure including an adjacent first region and a second region is provided. The displaying units have a predetermined-cutting region therebetween. Each displaying unit includes a peripheral circuit region and a display region having pixels. The ESD protection structure disposed on the predetermined-cutting region, located in the peripheral circuit region, and connecting the display region includes a first patterned conductive layer disposed on the first region and having an end away from the predetermined-cutting region, a first patterned dielectric layer disposed on the first patterned conductive layer and the substrate and having a first opening exposing a portion of the first patterned conductive layer, a patterned transparent conductive layer disposed corresponding to the predetermined-cutting region and connecting the first patterned conductive layer, and a second patterned dielectric layer covering the patterned transparent conductive layer and the substrate.

Methods of manufacturing master, pixel array substrate and electro-optical device

An electrophoresis display panel including an active device array substrate and an electrophoresis display film is provided. The active device array substrate includes a plurality of active devices and a shielding pattern. The electrophoresis display film is disposed on the active device array substrate. The electrophoresis display film includes a conductive layer, a dielectric layer and a plurality of electrophoresis display mediums. The dielectric layer is disposed on the conductive layer and has a plurality of micro-cups arranged in area array. The dielectric layer is between the conductive layer and the active device array substrate. Light passing through the dielectric layer is prevented from irradiating onto the active devices by the shielding pattern. In addition, the electrophoresis display mediums are filled within the micro-cups, respectively.

Electrophoresis display panel

A thin film transistor (TFT) and a fabricating method thereof are provided. The TFT includes a channel layer, an ohmic contact layer, a dielectric layer, a source, a drain, a gate, and a gate insulating layer. The channel layer has an upper surface and a sidewall. The ohmic contact layer is disposed on a portion of the upper surface of the channel layer. The dielectric layer is disposed on the sidewall of the channel layer, and does not overlap with the ohmic contact layer. The source and the drain are disposed on portions of the ohmic contact layer and the dielectric layer. A portion of dielectric layer is not covered by the source or the drain. The gate is above or below the channel layer. The gate insulating layer is disposed between the gate and the channel layer.

Fabricating method of a thin film transistor having a dielectric layer for inhibiting leakage current

A bottom gate thin film transistor and an active array substrate are provided. The bottom gate thin film transistor includes a gate, a gate insulation layer, a semiconductor layer, a plurality of sources and a plurality of drains. The gate insulation layer is disposed on the gate. The semiconductor layer is disposed on the gate insulation layer and located above the gate. An area ratio of the semiconductor layer and the gate is about 0.001 to 0.9. The sources are electrically connected with each other, and the drains are electrically connected with each other.

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Taipei, Taiwan

Pei-Ming Chen