Intel Corporation

Myson Technology Inc.

Knights Technology, Inc.

Pei-Lin Pai

Fu-Chieh Hsu

Chiu H Ting

A planar interconnect using selective, electroless deposition of a metal such as copper into interconnect channels is disclosed. A first dielectric layer is deposited on the surface of a substrate, such as an integrated circuit wafer. Thereafter, a second dielectric layer is formed on the first dielectric layer. Then a photoresist layer is spun on the top surface of the second dielectric layer. Channels are formed in the dielectric layers by patterning and etching the composite dielectric layers. Silicon atoms are implanted in the bottom of the interconnect channels and then the metal layer is selectively, electrolessly deposited to fill the channels in the first dielectric film, thus forming a level of interconnect. This process is repeated to form subsequent levels of interconnect.

Fully planar metalization process

An integrated circuit of the present invention comprises antifuse elements which have been fabricated by depositing at under 500.degree. C. an antifuse layer approximately 30 nanometers to 400 nanometers between layers of titanium (Ti), said antifuse layer comprising a stoichiometric or off-stoichiometric amorphous silicon-based dielectric layer, such that a heating of the said antifuse layer in excess of 500.degree. C. by electrical or energy beam means will cause a chemical reduction reaction between the titanium and silicon-dioxide layers that yields more Ti.sub.5 Si.sub.3, TiSi, and/or TiSi.sub.2 than is yielded TiO, Ti.sub.2 O.sub.3, Ti.sub.3 O.sub.5, and/or TiO.sub.2, and such that there results a conductive compound between said titanium layers which constitutes a short circuit.

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Cupertino, CA, United States of America

Pei-Lin Pai