Mediatek Corporation

Pei-Kuei Tsung

Yao-Sheng Wang

Chih-Wei Chen

Sung-Fang Tsai

Chih-Wen Goo

Yu-Sheng Lin

Shou-Jen Lai

Po-Chun Fan

Cheng-Lung Jen

Ming-Hao Liao

Yu-Cheng Tseng

Kuo-Chiang Lo

Chien-Hung Lin

Shih-Chin Lin

Ying-Chieh Chen

Wai Mun Wong

Tung-Chien Chen

Chun Chen Lin

Shih-Che Chen

Cheng Lung Jen

Chia-Da Lee

Yan-Hong Lu

Ming-En Shih

Chao-Min Chang

Ping-Yuan Tsai

Chia-Ching Lin

Chiani Lu

Kuan-Yu Chen

Po-Yu Chen

Hung-Jen Chen

Chi-Ming Chen

Chien-Yu Huang

Shih-Wei Hsieh

Chiung-Fu Chen

Chien-Ping Lu

Hung-Wei Wu

Chih-cheng Chen

ShengJe Hung

Jia-Yang Chang

Kuo-Chen Huang

Shu-Hsin Chang

Po-Hua Huang

Meng-Hsuan Cheng

Chun-Shen Liu

Chia-Hsien Chou

Tsung-Shian Huang

Pao-Hung Kuo

Yu-Lin Hou

Chia-Chi Chang

Yang-Yao Lin

Ken-Fu Liang

Mu-Fan Murphy Chang

Jen Cheng Lung

Shao-Yi Wang

Huang Tsung-Shian

Hsiao-Chien Chiu

Chun Hsien Wu

Hsin-Min Peng

Tsu Jui Hsu

Chia-Ni Lu

You Yu Nian

Mingen Shih

Yu Chieh Lan

Chih-wei Chen

A system receives a neural network model that includes asymmetric operations. Each asymmetric operation includes one or more fixed-point operands that are asymmetrically-quantized from corresponding floating-point operands. The system compiles a given asymmetric operation of the neural network model into a symmetric operation that includes a combined bias value. A compiler computes the combined bias value is a constant by merging at least zero points of input and output of the given asymmetric operation. The system then generates a symmetric neural network model including the symmetric operation for inference hardware to execute in fixed-point arithmetic.

Compiling asymmetrically-quantized neural network models for deep learning acceleration

A booster engine enhances the quality of a frame sequence. The booster engine receives, from a first stage circuit, the frame sequence with quality degradation in at least a frame. The quality degradation includes at least one of uneven resolution and uneven frame per second (FPS). The booster engine queries an information repository for reference information on the frame, using a query input based on at least a region of the frame to obtain a query output. The booster engine then applies a neural network to the query input and the query output to generate an optimized frame, and sends an enhanced frame sequence including the optimized frame to a second stage circuit.

Frame sequence quality booster using information in an information repository

The quality of a frame sequence is enhanced by a booster engine collaborating with a first stage circuit. The first stage circuit adjusts the quality degradation of the frame sequence when a condition in constrained resources is detected. The quality degradation includes at least one of uneven resolution and uneven frame per second (FPS). The booster engine receives the frame sequence from the first stage circuit, and generates an enhanced frame sequence based on the frame sequence for transmission to a second stage circuit.

Frame sequence quality booster under uneven quality conditions

A system produces a dolly zoom effect by utilizing side view information. The system first captures a main image at a main location. The main image includes at least a foreground object of a given size and a background. The system calculates one or more side view locations based on a zoom-in factor to be applied to the background and an estimated size of the foreground object. The system then guides a user to capture one or more side view images at the one or more side view locations. The foreground object of the given size is superimposed onto a zoomed-in background. Then the side view information is used by the system to perform image inpainting.

Automatic dolly zoom image processing device

A device produces a dolly zoom effect with automatic focal length adjustment. The device uses a camera to capture an initial image including at least a foreground object and a background. The device includes a size tracking circuit to identify the size of the foreground object in the initial image. The device further includes a focal length control circuit. The focal length control circuit calculates an adjusted focal length of the camera to maintain the size of the foreground object in subsequently captured images.

An image processing circuit performs super-resolution (SR) operations. The image processing circuit includes memory to store multiple parameter sets of multiple artificial intelligence (AI) models. The image processing circuit further includes an image guidance module, a parameter decision module, and an SR engine. The image guidance module operates to detect a representative feature in an image sequence including a current frame and past frames within a time window. The parameter decision module operates to adjust parameters of one or more AI models based on a measurement of the representative feature. The SR engine operates to process the current frame using the one or more AI models with the adjusted parameters to thereby generate a high-resolution image for display.

Image-guided adjustment to super-resolution operations

A frame interpolation method for generating a third image frame interpolated between a first image frame and a second image frame includes: performing motion estimation upon a first input image frame and a second input image frame, to obtain a single-directional motion, wherein the first input image frame is derived from the first image frame, and the second input image frame is derived from the second image frame; scaling the single-directional motion according to a time point of the third image frame, to generate a scaled motion; deriving a forward-warped result from a result of performing a forward warping operation and a first inverse operation upon the scaled motion; performing a second inverse operation upon the forward-warped result, to generate an inversed result; and generating the third image frame according to the first image frame, the second image frame, the forward-warped result, and the inversed result.

Method for performing frame interpolation based on single-directional motion and associated non-transitory machine-readable medium

Aspects of the disclosure provide a frame processor for processing frames with aliasing artifacts. For example, the frame processor can include a super-resolution (SR) and anti-aliasing (AA) engine and an attention reference frame generator coupled to the SR and AA engine. The SR and AA engine can be configured to enhance resolution and remove aliasing artifacts of a frame to generate a first high-resolution frame with aliasing artifacts and a second high-resolution frame with aliasing artifacts removed. The attention reference frame generator can be configured to generate an attention reference frame based on the first high-resolution frame and the second high-resolution frame.

AI frame engine for mobile edge

A video processing circuit includes an input buffer, an online adaptation circuit, and an artificial intelligence (AI) super-resolution (SR) circuit. The input buffer receives input low-resolution (LR) frames and high-resolution (HR) frames from a video source over a network. The online adaptation circuit forms training pairs, and calculates an update to representative features that characterize the input LR frames using the training pairs. Each training pair formed by one of the input LR frames and one of the HR frames. The AI SR circuit receives the input LR frames from the input buffer and the representative features from the online adaptation circuit. Concurrently with calculating the update to the representative features, the AI SR circuit generates SR frames for display from the input LR frames based on the representative features. Each SR frame has a higher resolution than a corresponding one of the input LR frames.

Online AI super resolution engine and operations

A method of feature extraction from an image can include receiving the image including pixels, generating confidence values corresponding to positions of the pixels in the image by an artificial intelligence (AI) based feature extractor, selecting a first position among the positions of the pixels in the image, a first confidence value among the generated confidence values at the first position being higher than a first threshold, and generating a final set of keypoint-descriptor pairs based on the confidence values corresponding to positions of the pixels in the image. The final set of keypoint-descriptor pairs includes at least two keypoint-descriptor pairs corresponding to the first position among the positions of the pixels in the image.

Feature extraction with keypoint resampling and fusion (KRF)

Aspects of the disclosure provide a device for processing frames with aliasing artifacts. For example, the device can include a motion estimation circuit, a warping circuit coupled to the motion estimation circuit, and a temporal decision circuit coupled to the warping circuit. The motion estimation circuit can estimate a motion value between a current frame and a previous frame. The warping circuit can warp the previous frame based on the motion value such that the warped previous frame is aligned with the current frame and determine whether the current frame and the warped previous frame are consistent. The temporal decision circuit can generate an output frame, the output frame including either the current frame and the warped previous frame when the current frame and the warped previous frame are consistent, or the current frame when the current frame and the warped previous frame are not consistent.

A video processing system includes an input port and a video processing circuit. The input port obtains device information of a display panel. The video processing circuit obtains an input frame and the device information, configures an image enhancement operation according to the device information, generates an output frame by performing the image enhancement operation upon the input frame, and transmits the output frame to the display panel for video playback.

Video processing system for performing artificial intelligence assisted picture quality enhancement and associated video processing method

A computing device operative to perform parallel computations. The computing device includes a controller unit to assign workgroups to a set of batches. Each batch includes a program counter shared by M workgroups assigned to the batch, where M is a positive integer determined according to a configurable batch setting. Each batch further includes a set of thread processing units operative to execute, in parallel, a subset of work items in each of the M workgroups. Each batch further includes a spilling memory to store intermediate data of the M workgroups when one or more workgroups in the M workgroups encounters a synchronization barrier.

Efficient work execution in a parallel computing system

An object detection apparatus includes a boundary box decision circuit and a processing circuit. The boundary box decision circuit receives lens configuration information of a lens, and refers to the lens configuration information to determine a bounding box distribution of bounding boxes that are assigned to different detection distances with respect to the lens for detection of a target object. The processing circuit receives a captured image that is derived from an output of an image capture device using the lens, and performs object detection upon the captured image according to the bounding box distribution of the bounding boxes.

Method and apparatus for performing object detection according to bounding box distribution that is determined by considering lens configuration

A processing unit performs multiply-and-accumulate (MAC) operations on asymmetrically quantized data. The processing unit includes a MAC hardware unit to perform the MAC operations on a first data sequence and a second data sequence to generate an asymmetric MAC output. Both the first data sequence and the second data sequence are asymmetrically quantized. The processing unit further includes an accumulator hardware unit to accumulate the first data sequence concurrently with the MAC operations to generate an accumulated output. The processing unit further includes a multiply-and-add (MAD) hardware unit to multiply the accumulated output with a second offset to generate a multiplication output, and to add the multiplication output, the asymmetric MAC output and a pre-computed value calculated before runtime to generate a final output. The second offset indicates an amount of asymmetry of the second data sequence with respect to zero.

Asymmetric quantization of multiple-and-accumulate operations in deep learning processing

Growing community of inventors

Taipei, Taiwan

Pei-Kuei Tsung