Nan Ya Technology Corporation

Pei-Ing Paul Lee

Chung-Yuan Lee

Chien-Li Cheng

Shian-Jyh Lin

Jeng-Ping Lin

Hsin-Chuan Tsai

Yi-Nan Chen

Chung-Lin Huang

Chiang-Lin Shih

Chi-Hui Lin

Hui-Min Mao

An-Hsiung Liu

Lin-Chin Su

Jih-Chang Lien

Ching-Nan Hsiao

Ming-Cheng Chang

Yuan-Hsun Wu

Wen-Bin Wu

Chung-Peng Hao

Chang Rong Wu

Meng-Hung Chen

Hung-Chang Liao

Tzu En Ho

Chung Peng Hao

Chung Lin Huang

Lee Chung Yuan

Hsien Wen Su

Yih-Ren Shao

Tzu-En He

Hsi-Hua Chang

Chi-Han Chang

Chih-Hsiang Wu

Wu Hsiung Chen

A memory device is provided. The memory device includes a substrate, a trench having an upper portion and a lower portion formed in the substrate, a trench capacitor formed in the lower portion of the trench, a collar dielectric layer formed on a sidewall of the trench capacitor and extending away from a top surface of the substrate, a first doping region formed on a side of the upper portion of the trench in the substrate for serving as source/drain, a conductive layer formed in the trench and electrically connected to the first doping region, a top dielectric layer formed on conductive layer, a gate formed on the top dielectric layer, an epitaxy layer formed on both sides of the gate and on the substrate and a second doping area formed on a top of the epitaxy layer for serving as source/drain.

Memory device with a length-controllable channel

A transistor structure includes a gate trench. The gate trench includes a bottle-shape bottom. The bottle-shape bottom includes a first conductive material wider than its top. The top includes a second material in a substrate, a gate structure on the gate trench and electrically connected to the first conductive material, a source/drain doping region adjacent to the gate trench and a gate channel between the source/drain doping region.

Transistor structure and method of making the same

A method of fabricating self-aligned recess utilizing asymmetric poly spacer is disclosed. A semiconductor substrate having thereon a first pad layer and second pad layer is provided. A plurality of trenches is embedded in a memory array region of the semiconductor substrate. Each of the trenches includes a trench top layer that extrudes from a main surface of the semiconductor substrate. Asymmetric poly spacer is formed on one side of the extruding trench top layer and is used, after oxidized, as a mask for forming a recess in close proximity to the trenches.

Electrical device and method for fabricating the same

A small-size (w&#x3c;0.5 micrometers) alignment mark in combination with a 'k1 process' is proposed, which is particularly suited for the fabrication of trench-capacitor DRAM devices which requires highly accurate AA-DT and GC-DT overlay alignment. The 'k1 process' is utilized to etch away polysilicon studded in the alignment mark trenches and to refresh the trench profile, thereby improving overlay alignment accuracy and precision.

Overlay alignment mark and alignment method for the fabrication of trench-capacitor dram devices

A memory structure disclosed in the present invention features a control gate and floating gates being positioned in recessed trenches. A method of fabricating the memory structure includes the steps of first providing a substrate having a first recessed trench. Then, a first gate dielectric layer is formed on the first recessed trench. A first conductive layer is formed on the first gate dielectric layer. After that, the first conductive layer is etched to form a spacer which functions as a floating gate on a sidewall of the first recessed trench. A second recessed trench is formed in a bottom of the first recessed trench. An inter-gate dielectric layer is formed on a surface of the spacer, a sidewall and a bottom of the second recessed trench. A second conductive layer formed to fill up the first and the second recessed trench.

Memory structure and method of making the same

A method of fabricating self-aligned gate trench utilizing TTO poly spacer is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad nitride layer is provided. A plurality of trench capacitors are embedded in a memory array region of the semiconductor substrate. Each of the trench capacitors has a trench top oxide (TTO) that extrudes from a main surface of the semiconductor substrate. Poly spacers are formed on two opposite sides of the extruding TTO and are used, after oxidized, as an etching hard mask for etching a recessed gate trench in close proximity to the trench capacitor.

Method for fabricating recessed gate MOS transistor device

A method for forming a semiconductor device is provided. The method comprises providing a substrate with recessed gates and deep trench capacitor devices therein. Protrusions of the recessed gates and upper portions of the deep trench capacitor devices are revealed. Spacers are formed on sidewalls of the upper portions and the protrusions. Buried portions of conductive material are formed in spaces between the spacers. The substrate, the spacers and the buried portions are patterned to form parallel shallow trenches for defining buried bit line contacts and capacitor buried surface straps. A layer of dielectric material is formed in the shallow trenches. Word lines are formed across the recessed gates. Bit lines are formed to electrically connect the buried bit line contacts without crossing the capacitor buried surface straps, and stack capacitors are formed to electrically connect with the capacitor buried surface straps. A semiconductor device is also provided.

Semiconductor device and method for making the same

A method of fabricating a semiconductor device having a trench gate is provided. First, a semiconductor substrate having a trench etch mask thereon is provided. The semiconductor substrate is etched to form a first trench having a first depth using the trench etch mask as a shield. Impurities are doped into the semiconductor substrate through the first trench to form a doped region. The doped region and the semiconductor substrate underlying the first trench are etched to form a second trench having a second depth greater than the first depth, wherein the second trench has a sidewall and a bottom. A gate insulating layer is formed on the sidewall and the bottom of the second trench. A trench gate is formed in the second trench.

Semiconductor device having a trench gate and method of fabricating the same

A method for forming a memory device with a recessed gate is disclosed. A substrate with a pad layer thereon is provided. The pad layer and the substrate are patterned to form at least two trenches. A deep trench capacitor is formed in each trench. A protrusion is formed on each deep trench capacitor, wherein a top surface level of each protrusion is higher than that of the pad layer. Spacers are formed on sidewalls of the protrusions, and the pad layer and the substrate are etched using the spacers and the protrusions as a mask to form a recess. A recessed gate is formed in the recess.

Method for forming a memory device with a recessed gate

A method for forming a memory device with a recessed gate is disclosed. A substrate with a pad layer thereon is provided. The pad layer and the substrate are patterned to form at least two trenches. A deep trench capacitor device is formed in each trench. The pad layer is recessed until upper portions of the deep trench capacitor devices are revealed. Spacers are formed on sidewalls of the upper portions of the deep trench capacitor devices. The pad layer and the substrate are etched using the spacers and the deep trench capacitor devices as a mask to form a recess, and a recessed gate is formed in the recess.

A method for forming a semiconductor device. A substrate is provided, wherein the substrate has recessed gates and deep trench capacitor devices therein. Protrusions of the recessed gates and upper portions of the deep trench capacitor devices are revealed. Spacers are formed on sidewalls of the upper portions and the protrusions. Buried portions of conductive material are formed in spaces between the spacers. The substrate, the spacers and the buried portions to form parallel shallow trenches are patterned to form parallel shallow trenches for defining active regions. A layer of dielectric material is formed in the shallow trenches, wherein some of the buried portions serve as buried contacts.

Method for forming a semiconductor device

A small-size (w&#x3c;0.5 micrometers) alignment mark in combination with a 'k1 process' is proposed, which is particularly suited for the fabrication of trench-capacitor DRAM devices which requires highly accurate AA-DT alignment. The 'k1 process' is utilized to etch away polysilicon studded in the alignment mark trenches and refresh the trench profile prior to AA pattern transferring, thereby improving wafer alignment accuracy and precision.

Growing community of inventors

Taipei Hsien, Taiwan

Pei-Ing Paul Lee