Taiwan Semiconductor Manufacturing Comp. Ltd.

Pei-Hung Chen

An-Min Chiang

Yeh-Jye Wann

Wen-Hsiang Tang

Shau-Tsung Yu

Shao-Yen Ku

Jui-Ping Chuang

Chun-Li Chou

Ming-Shuo Yen

Cheng-Hao Huang

Hsin-Pai Chen

Shinn-Sheng Yu

Chih-Ming Ke

Chiang-Jen Peng

Chuan-Chieh Huang

Jyh-Cheng You

Shih-Fang Chen

Yi-Jing Chu

Chih-Shih Wei

Sue-Mei Ku

Shaun-Tsung Yu

Some embodiments relate to a manufacturing method for a semiconductor device. In this method, a semiconductor workpiece, which includes a metal gate electrode thereon, is provided. An opening is formed in the semiconductor workpiece to expose a surface of the metal gate. Formation of the opening leaves a polymeric residue on the workpiece. To remove the polymeric residue from the workpiece, a cleaning solution that includes an organic alkali component is used. Other embodiments related to a semiconductor device resulting from the method.

Aqueous cleaning techniques and compositions for use in semiconductor device manufacture

Some embodiments relate to a manufacturing method for a semiconductor device. In this method, a semiconductor workpiece, which includes a metal gate electrode thereon, is provided. An opening is formed in the semiconductor workpiece to expose a surface of the metal gate. Formation of the opening leaves a polymeric residue on the workpiece. To remove the polymeric residue from the workpiece, a cleaning solution that includes an organic alkali component is used.

Aqueous cleaning techniques and compositions for use in semiconductor device manufacturing

A method of determining optical constants n and k for a film on a substrate is described. Optical measurements are preferably performed with an integrated optical measurement system comprising a reflectometer, spectral ellipsometer, and broadband spectrometer such as an Opti-Probe series tool from Therma-Wave. A beam profile reflectometer is employed to first determine the thickness of said film from a best fit of modeling data to experimental data. The thickness data is combined with the ellipsometer and spectrometer measurements to produce an experimental data output which is fitted with modeled information to determine a best fit of the data. Constants n and k are derived from the best fit of data. The method provides a higher accuracy for n and k values than by standard procedures which calculate n, k, and t simultaneously. The method may also be applied to bilayer or multi-layer film stacks.

Approach to improve ellipsometer modeling accuracy for solving material optical constants N & K

A new method for detecting blind holes in the contact layer of a multi-chip semiconductor test wafer makes use of the fact that if the hole is not a blind hole, a subsequent etch step extends the hole a predetermined distance into the layer immediately underlying the contact layer. After a predetermined number of holes have been etched through the contact layer and for a predetermined distance into the layer underlying the contact layer, the contact layer is stripped to expose the holes in the underlying layer. These holes are scanned optically by a commercial apparatus that ordinarily detects wafer defects that resemble the holes. The missing holes are detected by comparing the holes of different chips on the test wafer. The test is particularly useful with a high density plasma etch because these holes typically have a very small diameter in relation to the thickness of the contact layer.

Method for testing for blind hole formed in wafer layer

An improved seasoning process for a plasma etching chamber is described. This has been achieved by increasing the RF power to both the wafer and the walls of the chamber during seasoning. Additionally, the gas that is used is at a pressure of about 10 mTorr and has the following composition: chlorine about 90% and oxygen about 10%. By observing the optical emission spectrum during seasoning (notably lines due to the SiCl,species) it is confirmed that, under these conditions, seasoning is completed by using only a single wafer for about 100 seconds.

Process to season and determine condition of a high density plasma etcher

A method of etching a metal layer on a semiconductor device using an in-situ plasma cleaning step following the metal etch. The process begins by forming a metal layer over a semiconductor substrate. A photoresist mask is formed over the metal layer. The metal layer is patterned by dry etching unmasked areas of the metal layer in a plasma etching chamber. Polymer formations are formed during etching on the metal sidewalls and the walls of the plasma etching chamber. A novel plasma cleaning step is performed in-situ to partially remove the photoresist and to soften and partially remove the polymer formations formed on the metal sidewalls during etching. The plasma cleaning also partially removes polymer from the walls of the plasma etching chamber. The substrate is removed from the plasma etching chamber, and placed in an ashing chamber, and the remaining photoresist is removed. The substrate is removed from the ashing chamber and the remaining polymer formations are removed in a wet etch process.

Method of metal etching with in-situ plasma cleaning

A method of forming a number of closely spaced electrodes is described wherein covering the electrodes with a conformal layer of oxide or nitride deposited using plasma enhanced chemical vapor deposition does not result in the formation of restricted regions or keyholes between adjacent electrodes. The method uses de-focussing to form the electrode mask pattern in a layer of photoresist. The focal plane in which the electrode pattern is focussed is positioned a de-focus distance above the layer of photoresist. The de-focus method results in electrodes having a trapezoidal cross section wherein the bottom of the electrode is wider than the top of the electrode. The trapezoidal cross section avoids the formation of restricted regions or keyholes when the electrodes are covered with a conformal dielectric layer, such as a layer of oxide or nitride deposited using plasma enhanced chemical vapor deposition.

Opposite focus control to avoid keyholes inside a passivation layer

The present invention provides a method of manufacturing a read only memory that is code implanted late in the process after the first level metal thus reducing the turn around time to ship a customer order. The invention comprising the steps of: forming bit lines 125 and word lines 160 in a cell area 12A and MOS transistors in a peripheral area 13 of an integrated circuit; forming a first dielectric layer 300 over the surface; etching back the first dielectric layer 300 in the cell area; forming metal contacts 700 to the MOS devices in the peripheral areas 13; forming the second dielectric layer 320 over the resultant surface, storing the integrated circuit; and programming the ROM region 12A by the steps of forming a Code mask 340 with openings 340A from over portions of word lines in the cell area and implanting impurities through the openings 340A into substrate under the selected word lines 160 thereby programming the ROM device.

Post metal code engineering for a ROM

A method for manufacturing integrated circuit semiconductor device is provided for doping polysilicon formed on an N-well in a semiconductor substrate. Form a silicon oxide layer on the N-well. Then form a blanket polysilicon layer over the silicon oxide layer and pattern the polysilicon layer into a structure. Form a sacrificial oxide layer over the polysilicon structure. Then ion implant .sup.49 (BF.sub.2).sup.+ ions into the N-well and the polysilicon layer forming the source/drain regions and doping the polysilicon layer with P-type dopant thereby forming a doped polysilicon layer from the polysilicon layer. Then etch the sacrificial oxide layer away from the device. Form a polyoxide layer over the polysilicon structure. Then form a silicon oxide layer over the polyoxide layer followed by forming a glass layer thereover.

Oxidation method for removing fluorine gas inside polysilicon during

A method is described for forming P-channel field effect transistors having shallow source/drain junctions and improved reliability for CMOS circuits. The method involves forming both N-channel and P-channel FETs by alternate photoresist masking and ion implantation. The shallow junction self-aligned source/drain areas for P-channel FETs are formed by implanting boron difluoride (BF.sub.2) ions. In more conventional processing, the BF.sub.2 ions implanted in the P-channel FET gate electrodes during the source/drain implant results in outgassing of fluorine from the gate electrodes after the interlevel dielectric (ILD) layer is deposited. This can result in void formation, or delamination, at the interface between the gate electrode and the ILD. The current invention provides an improved process which uses a photoresist block-out mask to eliminate the implantation of the BF.sub.2.sup.+ ions in the P-channel FET gate electrodes during the formation of the self-aligned P.sup.+ source/drain regions. This prevents voids from forming at the gate electrode/ILD interface after the ILD layer is deposited and subsequent high-temperature processing steps are performed. The invention also reduces the enhanced boron diffusion in the P-FET gate oxide that can degrade the threshold voltage.

Method for preventing fluorine outgassing-induced interlevel dielectric

A method is described for forming P-channel field effect transistors having shallow source/drain junctions and improved reliability for CMOS circuits. The method involves forming both N-channel and P-channel FETs on the same substrate by alternate photoresist masking and ion implantation. The self-aligned source/drain areas for the P-channel FETs are formed by implanting boron difluoride (BF.sub.2) ions. In more conventional processing, the BF.sub.2 ions that are implanted in the P-channel FET gate electrodes during the source/drain implant results in out-gassing of fluorine from the gate electrodes after the interlevel dielectric (ILD) layer is deposited. This can result in void formation, or delamination, at the interface between the gate electrode and the ILD. The current invention provides an improved process which out-diffuses the fluorine atoms prior to depositing the ILD, and thereby prevents the formation of voids after the ILD is deposited and subsequent high-temperature process steps are performed.

Method for preventing delamination of interlevel dielectric layer over

A method of forming capacitors comprising polysilicon, polysilicon oxide, metal is described which significantly improves uniformity of capacitance across the silicon integrated circuit wafer and avoids damage to electrical contact regions. A first layer of polysilicon oxide is formed on a polysilicon first capacitor plate. The wafer is then dipped in a buffered oxide etch or subjected to a dry anisotropic etch. The etching conditions the polysilicon layer so that subsequent polysilicon oxide growth is very uniform and controllable. A second polysilicon oxide layer is then formed on the polysilicon first capacitor plate. A layer of silicon nitride is formed on the polysilicon oxide and a second capacitor plate is formed on the layer of silicon nitride completing the capacitor. Improved capacitance uniformity across the wafer is achieved and device damage is avoided.

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Hsin-Chu, Taiwan

Pei-Hung Chen