Macronix International Co., Ltd.

Tsinghua University

Pei-Ci Jhang

Chi-Pin Lu

Jung-Yu Shieh

Kuang-Chao Chen

Ling-Wuu Yang

Chun-Min Cheng

Chih-Hsiung Lee

Zong-Jie Ko

Sue-Lein Wang

Jeng Hwa Liao

Fu-Hsing Chou

Yumin Lin

Masaru Nakamichi

An integrated circuit structure includes a plurality of gate layers, a laterally stacked multi-layered memory structure, and a vertical channel layer. The gate layers laterally extend above the substrate and spaced apart from each other. The laterally stacked multi-layered memory structure extends upwardly above the substrate and through the gate layers and including a blocking layer, a charge storage stack, and a tunneling layer. The charge storage stack is on the blocking layer and including a first silicon nitride layer, a second silicon nitride layer, and a silicon oxynitride layer sandwiched between the first and second silicon nitride layers. The tunneling layer is on the charge storage stack. The vertical channel layer is on the laterally stacked multi-layered memory structure.

Memory device with multi-layered charge storage stack

A memory structure and a manufacturing method for the same are provided. The memory structure includes a charge trapping layer, a first silicon oxynitride tunneling film and a second silicon oxynitride tunneling film. The first silicon oxynitride tunneling film is between the charge trapping layer and the second silicon oxynitride tunneling film. A first atom concentration ratio of a concentration of a nitrogen atom to a total concentration of an oxygen atom and the nitrogen atom of the first silicon oxynitride tunneling film is 10% to 50%. A second atom concentration ratio of a concentration of a nitrogen atom to a total concentration of an oxygen atom and the nitrogen atom of the second silicon oxynitride tunneling film is 1% to 15%. The concentration of the nitrogen atom of the second silicon oxynitride tunneling film is lower than that of the first silicon oxynitride tunneling film.

Memory structure and manufacturing method for the same

Provided is a memory device including a substrate, a stack layer, a channel structure, a charge storage structure, a silicon nitride layer, and a buffer oxide layer. The stack layer is disposed over the substrate. The stack layer includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The channel structure penetrates through the stack layer. The charge storage structure surrounds a sidewall of the channel structure. The silicon nitride layer surrounds the conductive layers. The buffer oxide layer is disposed between the conductive layers and the silicon nitride layer.

3D memory device with silicon nitride and buffer oxide layers and method of manufacturing the same

A three-dimensional non-volatile memory including a substrate, a stacked structure and a channel layer. The stacked structure is disposed on the substrate and includes first dielectric layers, gates and charge storage structures. The first dielectric layers and the gates are alternately stacked. The charge storage structures are disposed at one side of the gates. Two adjacent charge storage structures are isolated by the first dielectric layer therebetween. Each of the charge storage structures includes a first oxide layer, a nitride layer and a second oxide layer sequentially disposed at one side of each of the gates. The channel layer is disposed on a sidewall of the stacked structure adjacent to the charge storage structures.

Three-dimensional non-volatile memory and manufacturing method thereof

A method of manufacturing an integrated circuit including forming trenches into the surface of a crystalline wafer and the trenches extending along a &#x3c;100&#x3e; lattice direction is disclosed. Such wafer can experience less deformation due to less stress induced when the trenches are filled using a spin-on dielectric material. Thus, the overlay issue caused by wafer shape change is resolved.

Method of improving localized wafer shape changes

A method of manufacturing a semiconductor device is provided. Gate structures are formed on a substrate, and a first dielectric layer having grooves is formed between two adjacent gate structures. An upper surface of the first dielectric layer is lower than an upper surface of the gate structures. Afterwards, an intermediate layer is formed to cover the gate structures, the first dielectric layer, and the grooves, and openings are formed therein. Each opening is formed between two adjacent gate structures, and the first dielectric layer is removed through the opening. Next, a second dielectric layer is formed on the intermediate layer, so as to define an air gap between two adjacent gate structures. Furthermore, a semiconductor device is provided.

Semiconductor memory array with air gaps between adjacent gate structures and method of manufacturing the same

A semiconductor device includes polysilicon layer and a metal silicide layer. The polysilicon layer is doped with carbon or phosphorous. The silicide layer is formed over the polysilicon layer.

Semiconductor device and methods of manufacturing

The present invention discloses a porous phosphor and manufacturing method of the same. The method includes manufacturing an organic-inorganic hybrid porous structure from solution comprising deep eutectic solvent, the 13group metal source, phosphorous acid source, and counter species source. With 4,4'-trimethylenedipyridine, the structure can be used as an intrinsic phosphor owning properties of photoluminescence without doping additional activator. The present invention also discloses a lighting device coated with the porous phosphor.

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Taipei, Taiwan

Pei-Ci Jhang