Intel Corporation

Lam Research Corporation

Pei-Chi Liu

Walid M Hafez

Chia-Hong Jan

Roman W Olac-Vaw

Rahul Ramaswamy

Hsu-Yu Chang

Ting Chang

Neville L Dias

Akhil N Singhal

Dustin Zachary Austin

Jeongseok Ha

Joodong Park

Chen-Guan Lee

Vadym Kapinus

Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

Non-planar I/O and logic semiconductor devices having different workfunction on common substrate

A plasma processing system is provided. The system includes a hydrogen gas supply and a hydrocarbon gas supply and a processing chamber. The system includes a first mass flow controller (MFC) for controlling hydrogen gas flow into the processing chamber and a second MFC for controlling hydrocarbon gas flow into the processing chamber. The system includes a plasma source for generating plasma at the processing chamber. The plasma is for etching SnO. The system includes a controller for regulating the first MFC and the second MFC such that a ratio of hydrocarbon gas flow to the hydrogen gas flow into the processing chamber is between 1% and 60% so that when SnHis produced during said etching SnO. The SnHis configured to react with hydrocarbon gas to produce an organotin compound that is volatilizable in a reaction that is more kinetically favorable than SnHdecomposition into Sn powder. Producing the organotin compound enables suction of Sn out of the processing chamber to prevent Sn powder from being deposited on the surfaces of the processing chamber during said etching SnO.

Method to clean SnOfilm from chamber

A method for cleaning SnOresidue from a processing chamber is provided as one embodiment. The method embodiment includes introducing hydrocarbon and hydrogen gas at a ratio of 1%-60% into a plasma processing system. The SnOresidue is etched from surfaces the processing chamber using plasma generated by a plasma source, which produces SnHgas. The SnHgas reacts with the hydrocarbon gas to produce an organotin compound that is volatilizable. The method further provides for evacuating the processing chamber of the organotin compound. The introduction of the hydrocarbon gas along with the hydrogen gas at the ratio of 1%-60% reduces a rate of SnHgas decomposition into Sn powder.

A MOS antifuse with an accelerated dielectric breakdown induced by a void or seam formed in the electrode. In some embodiments, the programming voltage at which a MOS antifuse undergoes dielectric breakdown is reduced through intentional damage to at least part of the MOS antifuse dielectric. In some embodiments, damage may be introduced during an etchback of an electrode material which has a seam formed during backfilling of the electrode material into an opening having a threshold aspect ratio. In further embodiments, a MOS antifuse bit-cell includes a MOS transistor and a MOS antifuse. The MOS transistor has a gate electrode that maintains a predetermined voltage threshold swing, while the MOS antifuse has a gate electrode with a void accelerated dielectric breakdown.

MOS antifuse with void-accelerated breakdown

IC device structures including a lateral compound resistor disposed over a surface of a substrate, and fabrication techniques to form such a resistor in conjunction with fabrication of a transistor. Rather than being stacked vertically, a compound resistive trace may include a plurality of resistive materials arranged laterally over a substrate. Along a resistive trace length, a first resistive material is in contact with a sidewall of a second resistive material. A portion of a first resistive material along a centerline of the resistive trace may be replaced with a second resistive material so that the second resistive material is embedded within the first resistive material.

Compound lateral resistor structures for integrated circuitry

Semiconductor device(s) including a transistor with a gate electrode having a work function monotonically graduating across the gate electrode length, and method(s) to fabricate such a device. In embodiments, a gate metal work function is graduated between source and drain edges of the gate electrode for improved high voltage performance. In embodiments, thickness of a gate metal graduates from a non-zero value at the source edge to a greater thickness at the drain edge. In further embodiments, a high voltage transistor with graduated gate metal thickness is integrated with another transistor employing a gate electrode metal of nominal thickness. In embodiments, a method of fabricating a semiconductor device includes graduating a gate metal thickness between a source end and drain end by non-uniformly recessing the first gate metal within the first opening relative to the surrounding dielectric.

Transistor gate metal with laterally graduated work function

An embodiment includes an apparatus comprising: a non-planar fin having first, second, and third portions each having major and minor axes and each being monolithic with each other; wherein (a) the major axes of the first, second, and third portions are parallel with each other, (b) the major axes of the first and second portions are non-collinear with each other, (c) each of the first, second, and third portions include a node of a transistor selected from the group comprising source, drain, and channel, (e) the first, second, and third portions comprise at least one finFET. Other embodiments are described herein.

Growing community of inventors

Portland, OR, United States of America

Pei-Chi Liu