Qualcomm Incorporated

Peeyush Kumar Parkar

Mohamed Hassan Abu-Rahma

Martin Saint-Laurent

David Anthony Kidd

Ramaprasath Vilangudipitchai

Animesh Datta

Rui Li

Seid Hadi Rasouli

Prayag Bhanubhai Patel

Venkat Narayanan

De Lu

Min Chen

Jay Madhukar Shah

Samy Shafik Tawfik Zaynoun

Saravanan Marimuthu

Sachin Bapat

Baldeo Sharan Sharma

Amit Patil

Aspects of the disclosure are directed to sensing integrated circuit (IC) Back End Of Line (BEOL) process corners. In one aspect, an apparatus for sensing IC BEOL process corners includes a ring oscillator including a plurality of ring oscillator stages configured to generate an output waveform with a frequency state; and a shield net circuit including a plurality of shield net stages corresponding to the plurality of ring oscillator stages, the shield net circuit having a toggle input. And, a method includes generating an output waveform with a frequency state using a ring oscillator that includes a plurality of ring oscillator stages; modifying a plurality of ring oscillator stage time delays through a coupling between a plurality of shield net stages and the plurality of ring oscillator stages; and selecting the frequency state using a toggle input of a shield net circuit which includes the plurality of shield net stages.

Back end of line (BEOL) process corner sensing

A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flip-flop. The circuit further includes a slave stage of the flip-flop responsive to the master stage. The circuit further includes an inverter responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage and to the slave stage of the flip-flop. The master stage is responsive to the control signal to control the slave stage.

Flip-flop with reduced retention voltage

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Bengaluru, India

Peeyush Kumar Parkar