Mosaid Technologies Corporation

Motorola Corporation

Pedro Ovalle

Alan S Roth

Oswald Anthony Becca

Dzung T Tran

Geoffrey B Hall

A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.

Double data rate output circuit

Double data rate output circuit and method

Double data rate output latch for static RAM device has edge-triggered flip-flop to output DDR signal to synchronize with a second clock signal

Synchronization circuit and method with transparent latches

A primary driver is activated to drive an output signal in response to an input signal. A reference signal is generated in response to the input signal. The output signal is compared to the reference signal. When the output signal lags the reference signal by a predefined amount an auxiliary driver is activated.

Load capacitance compensated buffer, apparatus and method thereof

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Austin, TX, United States of America

Pedro Ovalle