Delphi Technologies, Inc.

Delco Electronics Corporation

Pedro E Castillo-Borelly

Seyed R Zarabadi

Mark Russell Keyse

Gregory J Manlove

Abhijeet V Chavan

Jack L Glenn

James H Logsdon

Brian E Dewes

William Joseph Hulka

Michael P Donahue

Deron K Slaughter

A thermopile-based thermal detector is provided by a thermocouple, formed from a single sheet of material, which is made dissimilar with a P-doped and an N-doped junction electrically isolated via a naturally forming depletion region. The thermopile P-N sheet is uniform and planar, addressing stress and manufacturing issues. The usual non-active area of a conventional thermopile is significantly reduced or eliminated, and thus the output signal per unit diaphragm area of the detector is substantially increased, without the typical reduction in the signal-to-noise ratio. Also, a significant reduction in size of the thermal detector area is provided without a reduction in signal or signal-to-noise ratio. In an aspect, a second layer of thermocouples is axially positioned over, and connected with, a first layer of thermocouples. Additional axially stacked thermopiles can be provided within the same fabrication process. Signal processing circuitry may be electrically interconnected with the thermocouple.

P-N junction based thermal detector

An electrostatic discharge (ESD) protection device includes a first-type substrate, a second-type well formed in the substrate and a first-type well formed in the substrate. The second-type well includes a second-type+ region formed between first and second first-type+ regions. The first-type well is formed in the substrate adjacent a first side of the second-type well. The first-type well includes first and second first-type regions with a first-type+ region and a second-type+ region formed between the first and second first-type regions. The second-type+ region of the first-type well is formed between the first-type+ region of the first-type well and the second-type well.

Electrostatic discharge protection device

A method and apparatus for evaluating the functionality and sensitivity of an infrared sensor to infrared radiation. The method and apparatus are adapted for testing an infrared sensor having a diaphragm containing a heating element and a transducer that generates an output responsive to temperature. The method entails placing the infrared sensor in a controlled environment, and then exposing the diaphragm of the sensor to different levels of thermal radiation so as to obtain outputs of the transducer at different output levels. In the absence of exposure of the diaphragm to thermal radiation, flowing current through the heating element at different input levels so that the output of the transducer returns to the different output levels obtained using thermal radiation, the input difference between the input levels can be computed and used to assess the functionality and the sensitivity of the sensor.

Method and apparatus for testing an infrared sensor

A DC offset compensation circuit (,) for compensating for a DC offset voltage of a signal amplifier (,) includes a first sample and hold circuit (,) having an input receiving an amplifier output signal (VOUT,) and an output supplying the sampled and held output signal (VOUT,) to a non-inverting input of a comparator,A first digital-to-analog (D/A) circuit (,) is responsive to a number of digital input signals to produce an analog DC target signal at an output (V,) thereof. The analog DC target signal is provided to an input of a second sample and hold circuit (,) having an output supplying the sampled and held analog DC target signal to an inverting input of the comparator,The output of the comparator,is provided to an offset cancellation control circuit (,) including a state machine (,) and a counter circuit (,) operable to modify a count value (OFFDAC) thereof depending upon statuses of a number of input control signals (CLK,CLK,STRT, STP) and the comparator output signal (CO). A second D/A circuit has a number of digital inputs receiving the count value (OFFDAC) and producing at an output (VDCO) thereof an analog DC compensation signal corresponding thereto. The analog DC compensation signal is provided to a input (VDCO) of the signal amplifier (,) to thereby force the DC component of the amplifier output signal (VOUT,) near the analog DC target signal, thereby minimizing an aggregate DC offset voltage attributable to the signal amplifier (,).

DC offset compensation circuit for a signal amplifier

A cross-coupled latch circuit that is a one-time programmable latch that allows volatile temporary writes to the latch prior to permanent programming of the latch. The latch circuit includes first and second programmable FET devices that include poly-poly capacitators in series with the gate terminal of each device. A pair of PMOS FET devices combine with the programmable devices to make up the latch. The latch circuit includes other FET devices that are switched on and off depending on whether the latch is being permanently programmed, temporarily written to, or reset. A NAND gate is provided such that a logical high output on the NAND gate allows the first programmable device to be temporarily programmed with a logical one and permanently programmed with a logical zero. A NOR gate is provided such that a logical high on the NOR gate allows the second programmable device to be temporarily programmed with a logical zero and permanently programmed with a logical one.

Growing community of inventors

Kokomo, IN, United States of America

Pedro E Castillo-Borelly