Infineon Technologies Ag

Pedro Costa

Muhammad Hassan

Andre Roger

Romain Ygnace

Ketan Dewan

Pablo Yelamos Ruiz

A memory dispatcher, including an address decoder configured to decode a write address of received write data; a lockstep processor configured to generate, based on the decoded write address, primary and redundant memory write addresses and corresponding primary and redundant copies of the write data, if the decoded write address corresponds with a lockstep region of the memory; and a comparator coupled to the lockstep processor, and configured to compare the primary and redundant copies of the write data, and to compare the primary and redundant memory write addresses.

Memory dispatcher

A device for accessing memory configured to store an image data cube, wherein the memory has memory banks, and each memory bank has memory rows and memory columns. The device includes an input configured to receive a memory access request having a logical start address, which specifies a logical bank, a logical row, and a logical column, and a burst size; and a memory address generator configured to generate physical memory addresses based on the logical start address and the burst size, wherein any consecutive logical start addresses mapped to different memory rows are mapped to different memory banks.

Accessing a memory configured to store an image data cube

A modulator having a pulse density modulator configured to generate from bit stream information a Pulse Density Modulation (PDM) stream based on a PDM clock; and a bit stream adjuster configured to divide the PDM clock into a PDM multi-phase clock, adjust a duration of at least one pulse of the generated PDM stream by selecting a PDM clock phase of the PDM multi-phase clock for sampling the generated PDM stream, and output an adjusted PDM stream.

Pulse density modulation adjustment

A timer including a Pulse Width Modulation (PWM) signal generator configured to generate, based on a clock, a PWM signal having a first frequency resolution; a PWM time shifter configured to receive from the PWM signal generator the PWM signal having the first frequency resolution, and output a PWM signal having a second frequency resolution, wherein the second frequency resolution is higher than the first frequency resolution; and a control monitor configured to: control the PWM time shifter to time shift rising edges or falling edges of the PWM signal by an amount corresponding with a second frequency resolution.

Pulse width modulation signal frequency generation

In some examples, a device includes control circuitry configured to receive a first input signal, receive a second input signal, and cause gate driver circuitry to deliver a driver signal to a switch to cause the switch to deliver electrical power to an electrical load. In some examples, the control circuitry is further configured to determine whether the first input signal has an active value and determine whether the second input signal has an active value. In some examples, the control circuitry is also configured to cause the gate driver circuitry to change the driver signal across a switching cycle of the switch to increase or decrease the electrical power delivered by the switch to the electrical load in response to determining that the first input signal has the active value or in response to determining that the second input signal has the active value.

Control of switching regulator

The disclosure generally relates to a method and an apparatus for providing an adjustable high resolution dead time, and more specifically, to a method and an apparatus for inserting an adjustable high resolution dead time in a PWM signal. A method for inserting an adjustable high resolution dead time in a PWM signal includes receiving a clock signal at a delaying circuitry and generating, by the delaying circuitry, a plurality of phases, receiving the generated plurality of phases at a first multiplexer, and selecting and forwarding, by the first multiplexer, a first phase of the plurality of phases based on a first high resolution dead time value. The method further includes shifting a rising edge and/or a falling edge of the PWM signal using the received first phase forwarded by the first multiplexer.

Method and apparatus for providing an adjustable high resolution dead time

In various embodiments a controller for controlling the operation of a switched mode power supply is provided, the controller comprising: a first signal source configured to provide a first set of signals including a set signal and a clear signal, wherein the first set of signals may correspond to a first mode of operation of the switched mode power supply; a second signal source configured to provide a second set of signals including a set signal and a clear signal, wherein the second set of signals may correspond to a second mode of operation of the switched mode power supply; a selecting circuit coupled to the first signal source and to the second signal source, the selecting circuit being configured to select either the first set of signals or the second set of signals; a switching signal generating circuit coupled to the selecting circuit and configured to provide a switching signal to the switched mode power supply based on the set of signals received from the selecting circuit.

Growing community of inventors

Munich, Germany

Pedro Costa