Synopsys, Inc.

Pedja Raspopovic

Xiang Gao

Yi-Min Jiang

Philip H Tai

Jaime Wong

Lixin Shao

In one aspect, QoR metrics for different candidate macro placements are estimated using machine learning models. A set of candidate macro placements of hard macros within a circuit design is assessed by estimating a quality metric for each candidate macro placement, as follows. Model-specific estimates of the quality metric are predicted by applying different machine learning models to the candidate macro placements. The different machine learning models are trained using sets of completed macro placements for other circuit designs. The model-specific estimates of the quality metric are combined based on an applicability of (a) the set of macro placements used to train that model to (b) the set of candidate macro placements being evaluated.

Placing hard macros using machine learning predictions trained on different circuit designs

A system and method for generating physical design of an integrated circuit, based on schematic design. The system includes graphical user interface and integrated circuit design and layout system. The integrated circuit design and layout system creates and analyzes logical slices of the integrated circuit based on the schematic design; creates and edits macros based on the logical slices; and traces and analyzes data paths through the physical design based on the schematic design. The method includes providing the schematic design of the integrated circuit, and generating logical slices of the integrated circuit from the schematic design. The method also includes generating, grouping and manipulating macros, responsive to identification of multiple occurrences of logical slices. The method further includes performing data flow analysis to identify data paths for the physical design, quantifying weight indices for the data paths, and positioning objects in the physical design based on the weight indices.

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Cary, NC, United States of America

Pedja Raspopovic