Adeia Semiconductor Bonding Technologies Inc.

Silicon Storage Technology, Inc.

Adeia Semiconductor Technologies LLC

Pearl Po-Yee Cheng

Javier A DeLaCruz

Belgacem Haba

Rajesh Katkar

Neal Berger

Anne Pao-Ling Koh

George Chia-Jung Chang

David Edward Fisch

A memory structure is provided, including a NAND block comprising a plurality of oxide layers, the plurality of layers forming a staircase structure at a first edge of the NAND block, a plurality of vias disposed on the staircase structure of NAND block, two or more of plurality of vias terminating along a same plane, a plurality of first bonding interconnects disposed on the plurality of vias, a plurality of bitlines extending across the NAND block, and a plurality of second bonding interconnects disposed along the bitlines. The memory structure may be stacked on another of the memory structure to form a stacked memory device.

Apparatus for non-volatile random access memory stacks

The present disclosure provides for a stacked memory combining RAM and one or more layers of NVM, such as NAND. For example, a first layer of RAM, such as DRAM, is coupled to multiple consecutive layers of NAND using direct bonding interconnect (DBI®). Serialization and overhead that exists in periphery of the NVM may be stripped to manage the data stored therein. The resulting connections between the RAM and the NVM are high bandwidth, high pincount interconnects. Interconnects between each of the one or more layers of NVM are also very dense.

Non-volatile dynamic random access memory

An integrated circuit memory device has a plurality of memory cells arranged in a plurality of arrays. Each array has a plurality of rows, and a plurality of column lines, and a plurality of row lines connecting to the memory cells in each array. The memory cell in an array is addressable by a column line and a row line. A column address decoder receives a column address signal and selects one or more column lines of each array in response. A row address decoder receives a row address signal and selects a row line of each array in response. The memory device also has a plurality (k) of sense amplifiers, with one sense amplifier associated with each array, connectable to one or more column lines of the array and receives a signal therefrom supplied from an addressed memory cell. The memory device further has a register; and a control circuit. The control circuit receives a read command, and a clock signal, and in response to the read command activates a first plurality (j) of the plurality (k) of sense amplifiers (j&#x3c;k) for a time period sufficient to sense the signal on a connected column line associated with each of the plurality (j) of sense amplifiers. The control circuit latches the signal into the register; and deactivates the first plurality (j) of sense amplifiers; and serially outputs the signal from the register in response to the clock signal.

Power efficient read circuit for a serial output memory device and method

An integrated circuit memory device has an array of memory cells arranged in a plurality of rows and columns and a plurality of row lines and a plurality of column lines. Cells arranged in the same row are connected by a common row line, and cells arranged in the same column are connected by a common column line. Each cell in the array is addressed by an address signal which has a plurality of bits. A sense amplifier circuit is connectable to one or more of the plurality of column lines of the array. An address input terminal receives in series the plurality of bits of the address signal. Each of the column lines is connectable to a pre-charge voltage, in response to a read command. A decoder circuit receives the address signal and decodes the address signal as each of the plurality of bits is received and disconnects certain of the column lines to the pre-charge voltage in response to the decoding, and activates the sense amplifier circuit after all of the plurality of bits of the address signal are received.

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Los Altos, CA, United States of America

Pearl Po-Yee Cheng