Psemi Corporation

Broadcom Corporation

Payman Shanjani

Eric S Shapiro

Ravindranath D Shrivastava

Fleming Lam

Arya Behzad

Chengkai Luo

Hsin-Hsing Liao

Hao Jiang

Implementing a series gate resistor in a switching circuit results in several performance improvements. Few examples are better insertion loss, lower breakdown voltage requirements and a lower frequency corner. These benefits come at the expense of a slower switching time. Methods and devices offering solutions to this problem are described. Using a concept of bypassing the series gate resistor during transition time, a fast switching time can be achieved while the above-mentioned performance improvements are maintained.

Methods and devices to improve switching time by bypassing gate resistor

Methods and devices to reduce glitches in phase shifters implementing high isolation switches are disclosed. Such glitches occur at the output of the phase shifters when transitioning from one phase shift to another. The disclosed method implements delays in various steps of the phase shifter transitions. Exemplary embodiments implementing single-pole multi-throw are provided and exemplary performance of the disclosed methods are also presented. The described methods are also applicable to multi-step attenuators.

Glitch reduction in phase shifters

A positive-logic FET switch stack that does not require a negative bias voltage, and which can withstand application of a high voltage RF signal without requiring terminal capacitors. Some embodiments include a stack of FET switches, with at least one FET requiring a negative Vto turn OFF and configured so as to not require a negative voltage, series-coupled on at least one end to an end-cap FET that turns OFF when the Vof such end-cap FET is essentially zero volts, wherein at least one end-cap FET is configured to be coupled to a corresponding RF signal source and has a gate coupled to the corresponding RF signal source through an associated switch circuit. The switch circuit may include an NMOSFET and a PMOSFET, or a diode and an NMOSFET, or a diode and an NMOSFET and a PMOSFET.

High power positive logic switch

Methods and devices to reduce or remove slumps in power supplies are disclosed. The disclosed teachings can serve various applications, such as applications implementing RF switches. Using such teachings, an integrated method can benefit from two different modes of operation where either an external or an internal charge pump can be used to provide a desired negative voltage to various components within the integrated circuit. This can be done by disposing a larger load capacitor outside the integrated circuit and without compromising any die space requirement.

Power supply slump reduction methods and devices

Fail-safe methods and devices to protect the receiver of a transceiver in the event of an antenna failure are disclosed. The described devices implement inductive and capacitive elements to replace switches and can be used in any communication system or electronic circuit where the protection of a portion of the device from higher power signals is required. The inductive elements can be implemented using already existing inductors that are constituents of the receiver matching network. Configurations with off-chip capacitive or inductive components are also possible.

RF circuit protection devices and methods

An apparatus for reducing switching time of RF FET switching devices is described. A FET switch stack includes a stacked arrangement of FET switches and a plurality of gate feed arrangements, each coupled at a different height of the stacked arrangement. A circuital arrangement with a combination of a series RF FET switch and a shunt RF FET switch, each having a stack of FET switches, is also described. The shunt switch has one or more shunt gate feed arrangements with a number of bypass switches that is less than the number of FET switches in the shunt stack.

Methods and apparatus for reducing switching time of RF FET switching devices

Implementing a series gate resistor in a switching circuit results in several performance improvements. Few examples are better insertion loss, lower breakdown voltage requirements and a lower frequency corner. These benefits come at the expense of a slower switching time. Methods and devices offering solutions to this problem are described. Using a concept of bypassing the series gate resistor during transition time, a fast switching time can be achieved while the abovementioned performance improvements are maintained.

A common gate resistor bypass arrangement for a stacked arrangement of FET switches, the arrangement including a series combination of an nMOS transistor and a pMOS transistor connected across a common gate resistor. During at least a transition portion of the transition state of the stacked arrangement of FET switches, the nMOS transistor and the pMOS transistor are both in an ON state and bypass the common gate resistor. On the other hand, during at least a steady state portion of the ON steady state and the OFF steady state of the stacked arrangement of FET switches, one of the nMOS transistor and the pMOS transistor is in an OFF state and the other of the nMOS transistor and the pMOS transistor is in an ON state, thus not bypassing the common gate resistor.

Gate resistor bypass for RF FET switch stack

A high throw-count multiple-pole FET-based RF switch architecture that provides good RF performance in terms of insertion loss, return loss, isolation, linearity, and power handling. A common port RFC is coupled along a common path to multiple ports RFn. Embodiments introduce additional common RF path branch isolation switches which are controlled by state dependent logic. The branch isolation switches help to isolate the unused branch ports RFn and the unused portion of the common path from the active portion of the common path, and thereby reduce the reactive load attributable to such branches that degrades RF performance of the ports RFn 'closer' to the common port RFC. The branch isolation switches can also be used to reconfigure the switch architecture for a multiplex function as well as separate switch path banks for re-configurability of purpose, tuning, or varying switch throw counts and packaging options.

High throw-count RF switch

A switching network and associated method for operating within a transceiver are disclosed. The switching network has a timing control circuit that offsets the time at which a through switch and a shunt switch transition between on and off states. The output of the timing control circuit is an inverted and delayed version of a control signal applied to the input of the timing control circuit. Controlling the timing of the shunt switch provides a means to safely discharge any accumulated charge within the capacitance Cbetween the gate and source of transistors included within the through switch.

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San Diego, CA, United States of America

Payman Shanjani