Cadence Design Systems, Inc.

Pawan Kulshreshtha

Amit Dhuria

Krishna Prasad Belkhale

Hakan Yalcin

Vibhor Garg

Cyrus Soli Bamji

Igor Keller

Sharad Mehrotra

Rajarshi Mukherjee

Robert J Palermo

Mohammad S Mortazavi

Pradeep Yadav

Akash Khandelwal

Saulius Kersulis

Sri Harsha Venkata Pothukuchi

Jean Pierre Hiol

Chih-kuo Yu

An approach is described for a method, system, and product for deferred merge based method for graph based analysis to reduce pessimism. According to some embodiments, the approach includes receiving design data, static and/or statistical timing analysis data, identifying cells and interconnects for performing graph based worst case timing analysis where merger of signals is deferred based on one or more conditions to reduce pessimism, and generating results thereof. Other additional objects, features, and advantages of the invention are described in the detailed description, figures, and claims.

Method, system, and product for deferred merge based method for graph based analysis pessimism reduction

The present disclosure relates to a system for use in electronic circuit design. The system may include a computing device configured to receive, using at least one processor, an electronic design. The at least one processor may be further configured to generate a common path pessimism removal ('cppr') database configured to store one or more cppr tags obtained from an initial timing analysis of at least a portion of the electronic design. The at least one processor may be further configured to apply the one or more cppr tags during a block-level timing analysis.

Systems and methods for calculating common clock path pessimism for hierarchical timing analysis in an electronic design

A system and method for generating standard delay format (SDF) files is disclosed. For each timing closed hierarchical instance, timing arcs on internal register to register paths may be marked as zero delay arcs. If the zero delay causes a hold violation, an adjustment may be computed to fix the violation. If the adjustment does not cause a setup violation, the adjustment may be applied to the end point register.

System and method for generating reduced standard delay format files for gate level simulation

Electronic design automation systems, methods, and media are presented for hierarchical timing analysis with multi-instance blocks. Some embodiments involve generation of a combined timing context for instances of a multi-instance block. Such embodiments may merge timing context information with multi-mode multi-context (MMMC) views for different instances of a multi-instance block. Other embodiments involve efficient merging of instance timing contexts during block level static timing analysis. Various different embodiments involve separate or hybrid merged timing analysis based on a user selection.

Timing context generation with multi-instance blocks for hierarchical analysis

Disclosed are techniques for multi-mode, multi-corner physical optimization of electronic designs. These techniques identify an electronic design and a global set of views. Timing information is characterized with the global set of views for the electronic design. A set of active views is generated at least by pruning one or more views from the global set of views for a first node in the electronic design while maintaining the one or more views for a second node in the set of active views. The electronic design is then associated with the set of active views that is stored in a data structure in a non-transitory computer accessible storage medium.

Methods, systems, and articles of manufacture for multi-mode, multi-corner physical optimization of electronic designs

Electronic design automation systems, methods, and media are presented for hierarchical timing analysis with multi-instance blocks. Some embodiments involve generation of a combined timing context for all instances of a multi-instance block. Such embodiments may merge timing context information with multi-mode multi-context (MMMC) views for different instances of a multi-instance block. Other embodiments involve efficient merging of instance timing contexts during block level static timing analysis. Various different embodiments involve separate or hybrid merged timing analysis based on a user selection.

Hierarchical timing analysis for multi-instance blocks

A system and method are provided for common path pessimism removal or reduction (CPPR) in a timing database provided to guide transformative physical optimization/correction of a circuit design for an IC product to remedy operational timing violations detected in the circuit design. Pessimism is reduced through generation of a common path pessimism removal (CPPR) tree structure of branching nodes, and operational timing characteristics of each node. The CPPR tree structure is used to avoid exponential phases propagating in an exploratory manner through the system design, as well as the resultant memory footprint thereof. Additionally, back-tracing node-by-node through the circuit design for each and every launch and capture flip flop pair end point through each possible path thereof is avoided.

System and method for common path pessimism reduction in timing analysis to guide remedial transformations of a circuit design

A high accuracy method for transistor-level static timing analysis is disclosed. Accurate static timing verification requires that individual gate and interconnect delays be accurately calculated. At the sub-micron level, calculating gate and interconnect delays using delay models can result in reduced accuracy. Instead, the proposed method calculates delays through numerical integration using an embedded circuit simulator. It takes into account short circuit current and carefully chooses the set of conditions that results in a tight upper bound of the worst case delay for each gate. Similar repeating transistor configurations of gates in the circuit are automatically identified and a novel interpolation based caching scheme quickly computes gate delays from the delays of similar gates. A tight object code level integration with a commercial high speed transistor-level circuit simulator allows efficient invocation of the simulation.

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San Jose, CA, United States of America

Pawan Kulshreshtha