Texas Instruments Corporation

Pavol Balaz

Ferdinand Stettner

Hongcheng Xu

Methods, apparatus, systems and articles of manufacture are disclosed. An example apparatus includes a gate controller coupled between an input terminal and an intermediate node, the gate controller including a first transistor coupled between the input terminal and a first node; a second transistor coupled between the first node and the intermediate node; a third transistor coupled between the input terminal and the intermediate node; and a charge pump coupled to the intermediate node; a switching network coupled between the intermediate node and an output terminal, the switching network including a high-side drive (HSD) transistor having a HSD gate terminal coupled to the intermediate node, the HSD transistor coupled between an input voltage and a switch node.

Methods and apparatus to implement current limit test mode

A system includes a switching power converter, including a first transistor having a first gate, a first drain, and a first source, the first drain adapted to be coupled to a power supply. The switching power converter also includes a second transistor having a second gate, a second drain, and a second source, the second gate coupled to a second gate driver, the second source adapted to be coupled to ground, and the second drain coupled to the first source. The switching power converter also includes a third transistor having a third gate, a third drain, and a third source, the third gate adapted to be coupled to a current source, the third source coupled to a resistor, and the third drain coupled to the first gate. The switching power converter includes a capacitor coupled to the first drain and adapted to be coupled to the current source.

Closed loop commutation control for a switching power converter

Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor. The first transistor comprises a drain terminal coupled to an input voltage node, a source terminal coupled to a first node, and a gate terminal coupled to a second node. The second transistor comprises a drain terminal coupled to a third node, a source terminal coupled to a fourth node, and a gate terminal coupled to a fifth node. The third transistor comprises a drain terminal coupled to a sixth node, a source terminal configured to couple to a gate terminal of a switching transistor, and a gate terminal coupled to a seventh node. The first capacitor is coupled between the first node and the third node. The second capacitor is coupled between the fourth node and the sixth node.

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Freising, Germany

Pavol Balaz