Texas Instruments Corporation

Pavinkumar Ramasamy

Neeraj Bhardwaj

Madhusudan Sampath

Erfan Shirazian

William Joshua Bush

Arun Adoni

Janardhan Venkata Raju

Mahit Arun Warhadpande

Shimee Gupta

Shubham Mehrotra

Binoy Jose Maliakal

James Scott Mason

Goda Devi Addanki

Neha Vernekar

Yazdi Contractor

Apparatus for cooperating with a stationary integrated circuit test board. The apparatus includes a frame for positioning relative to a stationary integrated circuit test board, where the test board is for coupling to an integrated circuit device under test. The apparatus also includes a probe having a tip, and a processor-controlled actuator apparatus coupled to the frame and for moving the probe tip to selectively electrically contact a test point on the integrated circuit test board.

Integrated circuit spike check probing apparatus and method

Apparatuses and methods are disclosed for handling integrated circuits in automated testing. The handler apparatus includes an upper assembly that is selectively translatable above a testing surface and a lower bracket extending from and positioned below the upper assembly. The lower bracket forms a first opening, is selectively moveable upward and downward, and includes a rotatable finger extending downward to pick up and place an integrated circuit in a socket. The handier may further include an image sensor to detect potential error conditions, and a tool extending from the lower bracket to open and close a lid on the socket. The methods include sensing an image of an integrated circuit during certain phases of testing, analyzing the image to determine if the integrated circuit is positioned correctly, and correcting any detected error conditions before continuing with the automated testing.

Handling integrated circuits in automated testing

A nontransitory computer-readable program storage medium storing program instructions. The program, when executed by a processor, has the processor capable of receiving a set of input data, the input data relating to devices on a test board for testing a device under test. The program, when executed by a processor, also is capable of transforming the set of input data into test board mapping data. The test board mapping data comprises an ordered listing of potential test points along a path that couples to a conductive surface, wherein the potential test points are derived from at least one of the test board attributes. Further, the program, when executed by a processor, is capable of identifying a selected test point from among the one or more potential test points, the selected test point for spike check probing of the device under test.

Integrated circuit spike check test point identification apparatus and method

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Bengaluru, India

Pavinkumar Ramasamy