Honeywell International Inc.

Pavel Zaykov

Larry James Miller

Srivatsan Varadarajan

Lucie Matusova

Chittaranjan Kashiwar

Peter Mathia

Humberto Carvalho

Examples of computing systems that include I/O device(s) that respect an existing hardware resource partitioning in a modern computing platform are provided. The computing systems include at least one CPU having multiple cores and one or more CPU caches. The computing system also includes a main memory having locations, where each location maps to a set in the one or more CPU caches. A first subset of locations is partitioned for thread(s) of a first application and assigned to non-contiguous memory locations of the main memory. The computing system further includes an I/O device separate from the CPU that is configured to store I/O data in a second subset of locations that are different from the first subset of locations. The second subset of locations are non-contiguous memory locations of the main memory that are separated in address space according to a predefined pattern.

Input/output device operational modes for a system with memory pools

Systems and methods for regulating memory utilization for coprocessors are provided. In one embodiment, a computing system comprises: a processor; a compute processor configured to execute one or more kernels; a memory coupled to the processor and the compute processor. The system is configured to: allocate at least one task memory transaction quota to at least a first set of tasks executed on a first core of the processor; allocate at least one compute processor memory transaction quota for executing the kernels on the compute processor; execute within a first timing window iteration the first set of tasks and the kernels, wherein the kernels are executed during the first timing window iteration until the compute memory transaction quota is depleted; and regulate a rate of memory transaction access by the one or more kernels to the memory when the first set of tasks are executing on the processor.

Systems and methods for regulating memory utilization for coprocessors

Systems and methods for thermal management of computing systems are provided. The systems and methods described herein guarantee a thermal envelope of a computing system while preserving the compute and render performance capabilities of the computing system by implementing a thermal-aware scheduling policy, adjusting an amount of available memory bandwidth to computing resources, adjusting an amount of memory utilization by one or more applications executed by the computing resources, and/or allocating cache to workloads based on memory demands.

Systems and method for thermal management of computing systems

Examples of computing systems that include input/output (I/O) devices that respect an existing hardware resource partitioning in a modern computing platform are provided.

In one embodiment, a method for margin determination for a computing system with a real time operating system and priority preemptive scheduling comprises: scheduling a set of tasks to be executed in one or more partitions, wherein each is assigned a priority, wherein the tasks comprise periodic and/or aperiodic tasks; executing the set of tasks on the computing system within the scheduled periodic time window; introducing an overhead task executed for an execution duration controlled either by the real time operating system or by the overhead task; controlling the overhead task to converge on a point of failure at which a length of the execution duration of the overhead task causes either: 1) a periodic task to fail to execute within a deadline, or 2) time available for the aperiodic tasks to execute to fall below a threshold; and defining a partition margin corresponding to the point of failure.

Systems and methods for margin based diagnostic tools for priority preemptive schedulers

Techniques for determining worst-case execution time for at least one application under test are disclosed using memory thrashing. Memory thrashing simulates shared resource interference. Memory that is thrashed includes mapped memory, and optionally shared cache memory.

Systems and methods for simulating worst-case contention to determine worst-case execution time of applications executed on a processor

Systems and methods for outlier mitigation in safety-critical systems are provided. In one embodiment, a computer system comprises: a processor comprising one or more processing cores; a scheduling function that schedules the execution of applications, the applications each comprise threads; a contingency budgeting manager (CBM) that defines at least a first pre-determined set of threads from the threads of the applications and assigns a contingency budget pool to the first set of threads. The first set of threads are each scheduled by the scheduling function to execute on a first processing core. The CBM is further configured to monitor execution of each of the threads of the first set of threads to identify when a first thread is an execution time outlier. When the CBM determines that the first thread is an execution time outlier, it allocates additional thread execution time from the contingency budget pool to the first thread.

System and methods for contingency budgeting for time-partitioned systems

A method is provided. The method comprises: commencing a time window, where the time window has a fixed or variable time duration; determining a shared resource access quota for at least one time partition for the time window, where the shared resource access quota may vary by time window; allocating each determined shared resource access quota to a corresponding time partition for the window; determining if allocated shared resource access quota for any time partition in the time window has been met or exceeded; and if an allocated shared resource access quota for a time partition in the time window has been met or exceeded, then halting an executing process in the time partition.

Systems and methods for variable rate limiting of shared resource access

A computing system comprises at least one processing unit, at least one memory controller in communication with the processing unit, and a main memory in communication with the processing unit through the memory controller. A memory hierarchy of the computing system includes at least one cache, the memory controller, and the main memory. The memory hierarchy is divided into a plurality of memory pools. The main memory comprises a set of memory modules split in ranks each having a rank address defined by a set of rank address bits. Each rank has a set of memory devices comprising one or more banks each having a bank address defined by a set of bank address bits. A plurality of threads execute on the processing unit, and are assigned to the memory pools based on one or more memory partitioning techniques, including bank partitioning, rank partitioning, or memory controller partitioning.

Memory partitioning for a computing system with memory pools

A method comprises: receiving input data comprising a number of read and write uncached transactions, a transaction density, a number of active cores (N active cores) of the at least two cores, main memory address layout, and number of and an identifier for each of: banks and ranks in main memory, interconnects, cache pools, and memory controllers; defining all sets of active cores; defining up to N sets of memory pools; performing, for combinations of at least one set of active cores with each of at least one subset, the specified number of read and write uncached transactions with main memory at a specified transaction density for each defined combination of each active core combination and each defined memory pools; measuring the execution time of such performance for each combination; storing the execution time for each combination; and identifying at least one combination having a lower execution time.

Growing community of inventors

Brno, Czechia

Pavel Zaykov