Intel Corporation

Pavel Konev

Christopher P Mozak

Zvika Greenfield

Julius Yuli Mandelblat

Larisa Novakovsky

Ivan Herrera Mejia

Alexey Kostinsky

Leon Polishuk

Shrinivas Venkatraman

Alexey Chinkov

Manuel A Aguilar Arreola

Andrea R Vavra

Olga Fomenko

Systems and methods are disclosed for initialization of a processor. Embodiments relate to alleviating any BIOS code size limitation. In one example, a system includes a memory having stored thereon a basic input/output system (BIOS) program comprising a readable code region and a readable and writeable data stack, a circuit coupled to the memory and to: read, during a boot mode and while using a cache as RAM (CAR), at least one datum from each cache line of the data stack, and write at least one byte of each cache line of the data stack to set a state of each cache line of the data stack to modified, enter a no-modified-data-eviction mode to protect modified data from eviction, and to allow eviction and replacement of readable data, and begin reading from the readable code region and executing the BIOS program after entering the no-modified-data-eviction mode.

Systems and methods for enhancing BIOS performance by alleviating code-size limitations

Methods and apparatus for utilization of preset evaluation to improve input/output performance in high-speed serial interconnects are described. In some embodiments, performance of a link is evaluated at a plurality of equalization values and one of the plurality of equalization values is selected for the link based on comparison of a plurality of margin values that are to be determined for each of the plurality of equalization values. Other embodiments are also claimed and/or disclosed.

Preset evaluation to improve input/output performance in high-speed serial interconnects

Methods and apparatuses may provide for tracing the performance of BIOS from the start of its execution. A hardware device such as a hardware probe may be connected to the processor on a target board and used to gather and transfer data to a host computer without resort to a COM port.

Bios tracing using a hardware probe

Data pin mapping and delay training techniques. Valid values are detected on a command/address (CA) bus at a memory device. A first part of the pattern (high phase) is transmitted via a first subset of data pins on the memory device in response to detecting values on the CA bus; a second part of the pattern (low phase) is transmitted via a second subset of data pins on the memory device in response to detecting values on the CA bus. Signals are sampled at the memory controller from the data pins while the CA pattern is being transmitted to obtain a first memory device's sample (high phase) and the second memory device's sample (low phase) by analyzing the first and the second subset of sampled data pins. The analysis combined with the knowledge of the transmitted pattern on the CA bus leads to finding the unknown data pins mapping. Varying the transmitted CA patterns and the resulting feedbacks sampled on memory controller data signals allows CA/CTRL/CLK signals delay training with and without priory data pins mapping knowledge.

Training for command/address/control/clock delays under uncertain initial conditions and for mapping swizzled data to command/address signals

Growing community of inventors

Haifa, Israel

Pavel Konev