Silicon Laboratories Inc.

Pavel Konecny

Jinwen Xiao

Axel Thomsen

Xiaodong Wang

John M Khoury

Kenneth Wilson Fernald

Alan Lee Westwick

Clayton H Daigle

Shahram Tadayon

Wayne Thomas Holcombe

Scott Willingham

Praveen Kallam

Johnny Gudmund Bjornsen

Yeshoda Yedevelly

Ka Yin Leung

Miroslav Svajda

Ali Fawaz

Jean-Luc Nauleau

Robert Gordon Farmer

Dag Pettersen

An apparatus includes a circuit that has a normal mode of operation and a low-power mode of operation. The circuit consumes more power in the normal mode of operation than in the low-power mode of operation. The apparatus further includes a power-supply circuit. The power-supply circuit provides a normal supply voltage to the circuit in the normal mode of operation. The power-supply circuit includes a non-linear circuit to provide a compressed supply voltage to the circuit in the low-power mode of operation, wherein the normal supply voltage is greater than the compressed supply voltage.

Apparatus for power consumption reduction in electronic circuitry and associated methods

An apparatus includes an integrated circuit (IC). The IC includes a differencing comparator. The differencing comparator receives a differential input signal. The differencing comparator compares the differential input signal to a threshold value. The differencing comparator includes a transconductance circuit coupled to receive the differential input signal and to provide a differential output signal.

Apparatus for differencing comparator and associated methods

An integrated circuit (IC) includes a plurality of pads adapted to send or receive signals, and a plurality of mixed signal interface blocks, each of which is coupled to a corresponding pad in the plurality of pads. Furthermore, each mixed signal interface block in the plurality of mixed signal interface blocks is adapted to be configurable to provide selected functionality independently of the other mixed signal interface blocks.

Apparatus for mixed signal interface circuitry and associated methods

In one aspect, an apparatus includes a ready circuit to output a ready indicator when a supply voltage provided to the ready circuit and a voltage regulator is sufficient to operate the voltage regulator. In turn, the voltage regulator is to receive the supply voltage and output a regulated voltage, receive a first current from the ready circuit and control the regulated voltage based on the first current when the ready indicator is inactive. The apparatus further includes a bias circuit to receive the regulated voltage and generate one or more bias currents, which may be provided to an output circuit to output one or more bias outputs to one or more client circuits therefrom.

Bias circuit for generating bias outputs

A capacitor is charged synchronously with the beginning of an ON portion of a pulse width modulated (PWM) signal to generate a voltage across the capacitor using charging current sourced from an inductor on a primary side of a transformer. The voltage is supplied as a supply voltage to control circuitry in an integrated circuit used to generate the pulse width modulated signal. The charging is stopped when either the charging current goes above a predetermined charging current level or when the capacitor voltage goes above a predetermined capacitor voltage.

Synchronous VCC generator for switching voltage regulator

In an embodiment, a method includes: during a first portion of a cycle of a clock signal generated by an oscillator, pre-charging a first capacitor of a first switched capacitor stage until a first comparator determines that a first node voltage of the first switched capacitor stage is greater than a first reference voltage at a first reference voltage node; applying a second reference voltage to the first reference voltage node; and responsive to a first edge of the clock signal, charging the first capacitor until the first comparator determines that the first node voltage is greater than the second reference voltage at the first reference voltage node.

Relaxation oscillator

Techniques are disclosed relating to supplying a power supply voltage to a gate driver. In one embodiment, an apparatus is disclosed that includes a first transistor configured to raise a voltage at a node and a second transistor configured to lower the voltage at the node. The apparatus further includes a first driver configured to receive a first power supply voltage, and to use the first power supply voltage to control a gate voltage of the first transistor. The apparatus further includes a second driver configured to receive a second power supply voltage, and to use the second power supply voltage to control a gate voltage of the second transistor. In such an embodiment, the apparatus includes a first regulator coupled to the first driver and configured to generate the first power supply voltage based on the second power supply voltage.

Boot-strap regulator for gate driver

An input digital signal is converted to an analog signal using a main digital to analog converter (DAC) and a sub DAC. An offset value is subtracted from the input digital signal to generate an offset adjusted digital signal. The main DAC converts the offset adjusted digital signal to a first analog signal. A second digital signal is generated based on the offset value and a correction factor determined, at least in part, during calibration of the main DAC. The sub DAC converts the second digital to a second analog signal, which when combined with the first analog signal, provides an analog representation of the input digital signal.

Digital to analog converter

A power supply including a switching voltage regulator detects a peak power fault if a peak power limit is exceeded during a switching cycle of the voltage regulator. A second fault condition exists if a second power limit, lower than the peak power limit, is exceeded over a second time period, longer than the first time period. The switching voltage regulator is stopped in response to either the first or the second fault condition. Responsive to the second fault condition, the switching voltage regulator may be stopped until AC power is cycled or until a predetermined time period has elapsed.

Continuous power protection

Techniques are disclosed relating to charging and discharging gates of transistors. In one embodiment, an apparatus includes first and second drivers. The first driver is configured to discharge a gate of a first transistor, and to send a charge indication to the second driver in response to reaching a Miller plateau for the first transistor. The second driver is configured to charge a gate of a second transistor above a threshold voltage in response to receiving the charge indication. In some embodiments, the second driver is configured to begin charging the gate of the second transistor to a voltage below the threshold voltage when the first driver begins discharging the gate of the first transistor begins, and to wait to charge the gate of the second transistor above the threshold voltage until the charge indication has been received.

Amplifier using master-slave control scheme

Techniques are disclosed relating to charging and discharging a gate of transistor. In one embodiment, an apparatus is disclosed that includes a driver configured to discharge a gate of a transistor. The driver is configured to discharge the gate at a first rate until reaching a Miller plateau for the transistor, and to discharge the gate at a second rate after reaching the Miller plateau. In such an embodiment, the first rate is greater than the second rate. In some embodiments, the driver is also configured to charge the gate of the transistor at a third rate until reaching a Miller plateau for the transistor, and to charge the gate at a fourth rate after reaching the Miller plateau, the third rate being greater than the fourth rate. In some embodiments, the apparatus is a class D amplifier.

Amplifier using fast discharging reference

A switching voltage regulator samples signals corresponding to a flyback voltage on an auxiliary winding on a primary side of the switching voltage regulator. The flyback voltage functions as feedback from the output voltage on the secondary side. On detection of presence of the flyback voltage, samples corresponding to the flyback voltage are stored until the flyback voltage falls below a threshold voltage. A history of N samples of the flyback voltage is thus maintained. A sample older than the most recently stored sample is used to generate control for generation of the output voltage of the switching voltage regulator. Use of the older sample ensures that the flyback voltage sample used is one that is close to, but before the current in the secondary winding goes to zero.

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San Jose, CA, United States of America

Pavel Konecny